When the manufacturer recommends some capacitors with specific values, can I choose caps with more capacitance? Will it give any advantage? For example decoupling caps at MCU power pins. Or LDO input and output caps.
Thanks
Electrical – Capacitors minimum value
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Your title asks about the value of the capacitors, and I think that has been adequately covered- you should match the nominal value to the specified load capacitance of the crystal (when in series with each other, and subtracting some allowance for input and stray capacitance).
The Q of a typical crystal resonator circuit is very high (maybe 100,000), and a small change in load capacitance won't affect the oscillation frequency by much. The equivalent "motional" capacitance of the resonator is quite high, so the pull effect of the load is small (typically measured in ppm/pF). If you are not using the crystal for a time keeping clock, it probably won't make much difference for you- it will vary with the crystal and load capacitance, but, say 5pF might make 30ppm or 100ppm difference in the oscillator frequency.
Since the capacitor might be 22pF, 5pF is a lot of change, so the tolerance and temperature coefficient is not very important. It's also cheap and easy to find almost perfect capacitors in the capacitance range used for load capacitors- ceramic NP0 types with tolerances of 5% are the cheapest and most available, and they're always rated for at least the voltage required (Vdd + 1.2V is certainly enough). Take the 27pF value- a Samsung CL10C270JB8NCNC is 5% tolerance, 50V, maximum drift of +/-30ppm/°C** and insulation resistance in the 10G range. All for $7.54 for a reel of 4,000 pieces, Digikey price. The difference between microwave and ordinary NP0 caps would not be noticed at 16MHz (except, of course, for the much higher price of the former). There are all kinds of complications (voltage coefficient, high temperature coefficient, microphonics, aging) associated with high value ceramic capacitors that don't apply much, if at all, to NP0 parts.
TL;DR Bottom line- if you use the most common NP0 ceramic capacitors in your favorite size, your circuit performance will not be limited by the capacitors in virtually all cases.
** Note that a 30ppm/K change of the load capacitor would likely contribute less than 0.1ppm/K change to the oscillation frequency (the temperature changes will be dominated by the crystal itself).
So you could fill a book with the answer to this question, in fact I think I have some on my shelf
Let’s run through your questions.
Should you use a 4 layer board instead of a 2 layer? I say absolutely yes, the cost argument to going 2 layer is a weak one at best compared to the advantages. Obviously it can be done, and is done, and in this devices case I see they placed VCC and GND right next to each other to make this easier to accomplish. So while I would go 4 layer, you can probably get away with 2 if you want.
Why decouple?
Now without going too deep consider the goal of decoupling your processor. You are trying to supply a stable voltage to it despite the fact that it has dynamic current demands. When your processor is active for instance and its transistors switch they are requesting more current. This current is a change, an increase to the current draw at steady state. Now you have a changing current but where are you going to get that current from?
Well first there’s a little decoupling on the die, but then it tries to pull it through the package power and gnd pins. It wants to get at that capacitor you placed outside of your device but before it gets there it has to travel through the bond wires and or package substrate, out the pins, and down your traces. All of this contributes to the inductance, and ultimately the impedance of the path from the die inside the chip to the capacitor.
Why does this matter? Well because an inductor “resists” changes in current consequently its impedance increases as frequency increases. That’s a simplification, but what happens when you try to drag that change in current through your package and routing is that the inductance limits the amount of current you can get.
So your goal when placing your decoupling capacitors should always be to minimize the impedance, and thus the inductance from the pin to your cap. Now with a QFP package like this you may find the shortest possible connection is right at the pins, with a 4 layer board and a BGA it might be directly underneath, but in practice you can achieve even lower impedance on top layers as well.
Don’t ignore GND either. Current flows in a loop, it does you no good to have a super short path to VCC and long winding path to GND. So if you’re going 2 layer I would put the caps parallel, as close as possible to GND and VCC, route directly to the pins, and then bring power and gnd into the caps. Your goal is to minimize the loop size. More 4 layer arguments and selection
The goal of what we call Power distribution network design is to minimize the impedance across the range of frequencies that your chip will request. To that end having a nice fat GND and VCC plane leading from your caps/part to your regulator will be a much lower impedance path for your lower frequency down to DC. Short of that fat wide traces are recommended if you can.
Cap selection For this processor and your board I think 0.1uF 402s and 0805 10uF are a good choice. The smaller package size helps you have a smaller loop size. I can do 201 by hand, never bought a 1005, but it is easier with a microscope. For more complex designs we select a range of decoupling capacitors to cover the range of frequencies that the part might demand from us. Blindly doing this as in just using 0.1uF, 0.01uF, and 0.001uF as is often suggested can lead to nasty anti resonance peaks giving you high impedance and certain frequencies Again this is a simplification, but I don’t think digging into that here will help you. Interesting to note that placing the 10uF capacitors further away is ok as their role in this design is for the lower frequencies where the impedance caused by the trace inductance will be lower. Also the frequency range you can effectively decouple to is limited by the impedance of the package we discussed earlier.
Actual part selection There are tons of capacitors out there, and usually we don’t make specific part recommendations. But I would look for a 402 0.1uF ceramic capacitor with maybe an X7R temperature coefficient, and a voltage rating double your VCC. Here’s an example of one I have on a BOM
Your questions
OK long winded response I guess but sometimes if you get why something is done it makes it easier to decide how to do it.
So you say:
2 layer board: Seems ok for this, I always prefer a 4 as explained above. There are other benefits such as controlled impedance of traces, less noise, easier to pass emi. I don’t know what your board will do but without reference planes your traces return current will be forced to all follow whatever GND wires it can find. Gets a little messy.
GND pours: Meh it will help balance the copper on top and bottom layers for etching and re-flow, but really you’ll carve it up so much with traces it won’t do you that much good. Better to concentrate on getting power to that chip with as low an impedance as possible. Maybe you can figure out how to run VCC and GND as two copper pours?
Components on top: OK doesn’t really matter, in this case better to have decoupling on top than to go through vias to the bottom. If you are hand assembling it doesn’t really matter, but it would be cheaper to manufacture.
Traces on top and bottom: Definitely you probably won’t get away without this.
Decoupling: I talked about this at length.
Ah what else oh the ferrite, I didn’t see that in the app note. I’m assuming maybe it’s used to isolate one of the more sensitive VCC pins, maybe a PLL or an ADC. And it actually goes VCC supply -> Ferrite -> VCC Pin, with the cap from VCC pin to GND? If so that makes sense it’s probably just a little filter.
Got any questions? Just ask, it's hard to put everything you need to know about decoupling in one answer but hopefully this helps.
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Best Answer
The question has two parts: caps on LDO, and decoupling caps on MCU. Because these functional blocks are physically separated on a PCB and linked via wires (or planes), there is some degree of de-coupling, and frequently there is an intentional de-coupling in a form of ferrite beads and inductors. So the question of cap selection can be treated separately, in first approximation.
For LDO, is is advisable to use manufacturer's specifications. Always. Each LDO is designed to meet certain specific needs. Some LDO are designed to be "capless", to better suite portable devices with explicit power gating. Less caps allow for faster power-on time and less waste on power-off. These LDO will be unstable (or make overshoots) with bigger load caps. Some older LDOs need certain range of ESR in the load cap. Thus some excellent MLCC with a milliohm-ESR will make it unstable, so some lesser-quality aluminum or tantalum cap is needed to fix this. Or you would need to add an explicit 1-Ohm resistor in series with ceramic cap. Some even older LDOs require hundreds of uF to be stable.
For the MCU, bigger capacitors are likely not good. The purpose of these caps is to mitigate short spikes of current that a (badly designed) MCU can demand during intricacies of their running software, which can run in 10-100-1000MHz range. Bigger caps (like 1uF) are effectively inductors at frequencies above 10MHz, and will fail to do the job. To better accommodate the entire spectrum of power spikes, a network of caps is frequently used, say 100nF, 5nF, 220pF in parallel.
In any case it will save you a lot of time and troubles if you follow manufacturer's suggested layout and bypass network topology and follow the suggested BOM, without much of "choosing".