There's a single surface of semiconductor, so doesn't matter how many conductor layers you have, you need to go down to ground level at every conductor terminal. Note, not the conductors is the heart of circuit, but silicon devices on surface of a chip. You cannot stack transistors one above another with current technology. This very limits IC grow to third dimension. So it's still 2D.
To be 3D, IC technology needs method to make and interconnect devices in bulk of semiconductor or method to make lots of stacked semiconductor films.
First of all, you have to define what Moore's law means. Initially, Moore defined it as the number of components on a single IC.
This is easy to achieve by increasing the size of the die (the piece of silicon). But as there are also limits to this size (mainly cost and yield, but also signal propagation delay for fast ICs), you try to shrink the ICs.
So, today Moore's law is often defined as number of components per area. Sometimes it is also used for performance per CPU or similar, but this is not the intention of the law.
Now about your question:
If there is a technology to produce an IC, it first may be not be perfect. The contours of the structures are not very precise / straight, but the production has a good yield. During production, experience and small improvements lead to a higher precision, which allows you to shrink your structure.
This will not go on forever, because once you will encounter insolvable problems with your current technology. To overcome this problems, you need to apply major changes to the existing techology, or even use a new technology.
However, the question is if there is a final, hard limit. This 5nm is a guess for such a limit. But this limit bases on limits of current technology and expected / extrapolated limits for future technologies or just physical limits. Silicon atoms have a diameter of ~0.2nm, so a 5nm structure is about 20 atoms wide. So, this limit sounds reasonable. But if you change to other materials or use other physical effects, you may be able to overcome this limit.
Finally, there is a big difference between being able to produce a 1nm structure in the lab and producing an IC with billions of 1nm structures. As said above, the yield may be 1% at the moment, which is fine for demonstration of the process, but bad for production. Also, I don't know how they created this transistors, but may be, this technology is not feasible for more complex structures and mass production. (Using a scanning force microscope, you can push around atoms and build a single transistor, but not a whole chip)
This means, though we can already build a transistor in 1nm technology, we should not expect it to replace the current 28nm (?) nor the future 5nm directly.
Best Answer
Chip fabrication is divided into two steps, FEOL and BEOL
The manufacturer has to start with FEOL where all the components (transistors, resistors, capacitors) are created in the silicon.
Only when FEOL is done, BEOL can start.
BEOL is the step where all the components on the chip are connected to make circuits. This is also the step which will define the mask ROM data in your chip.
Often FEOL is more complicated and takes more time than BEOL so that is why although they've started, they can still allow for changes in the BEOL part of the design.
Probably your chip vendor has split the process in two, they first make the FEOL masks and start processing. When the FEOL is almost finished they make the masks needed for BEOL. Making the BEOL masks already at the start of FEOL makes little sense as they're not needed until FEOL is finished and BEOL starts.
This also allows for ROM data updates as that is BEOL only.
So the mask needed to program the data on the chip is probably not made yet so they can easily change it even though they started making the masks already. But those will be FEOL masks, not the BEOL masks with the ROM data.