First of all, you have to define what Moore's law means. Initially, Moore defined it as the number of components on a single IC.
This is easy to achieve by increasing the size of the die (the piece of silicon). But as there are also limits to this size (mainly cost and yield, but also signal propagation delay for fast ICs), you try to shrink the ICs.
So, today Moore's law is often defined as number of components per area. Sometimes it is also used for performance per CPU or similar, but this is not the intention of the law.
Now about your question:
If there is a technology to produce an IC, it first may be not be perfect. The contours of the structures are not very precise / straight, but the production has a good yield. During production, experience and small improvements lead to a higher precision, which allows you to shrink your structure.
This will not go on forever, because once you will encounter insolvable problems with your current technology. To overcome this problems, you need to apply major changes to the existing techology, or even use a new technology.
However, the question is if there is a final, hard limit. This 5nm is a guess for such a limit. But this limit bases on limits of current technology and expected / extrapolated limits for future technologies or just physical limits. Silicon atoms have a diameter of ~0.2nm, so a 5nm structure is about 20 atoms wide. So, this limit sounds reasonable. But if you change to other materials or use other physical effects, you may be able to overcome this limit.
Finally, there is a big difference between being able to produce a 1nm structure in the lab and producing an IC with billions of 1nm structures. As said above, the yield may be 1% at the moment, which is fine for demonstration of the process, but bad for production. Also, I don't know how they created this transistors, but may be, this technology is not feasible for more complex structures and mass production. (Using a scanning force microscope, you can push around atoms and build a single transistor, but not a whole chip)
This means, though we can already build a transistor in 1nm technology, we should not expect it to replace the current 28nm (?) nor the future 5nm directly.
Best Answer
I'd say that proper digital IC design is not done bottom-up but top-down !
You start with a specification of the function which you need. You get this from someone else or write your own.
Then you translate that into Verilog or VHDL and simulate until it does what you think it should do.
Then you generate the netlist from the Verilog or VHDL.
Very likely you will simulate that netlist to verify that it works as expected.
From the netlist a layout is synthesized using the IC manufacturer's libraries. These libraries contain the layouts of all the gates needed (Inverters, AND, OR gates etc) and it contains information on the delay of these gates.
So normally digital designers are not bothered by the actual transistors as the gates are blocks which are ready to use.
The synthesized layout is send to the manufacturer for further processing and mask-making.
The wafers are then processed using these masks.
What I wrote might be wrong in some respects as I am an Analog IC designer, not a digital one. When I need some digital I just draw a schematic with gates directly. This is only suitable for simple functions with only a few gates. I do sometimes layout my own transistor level gates though.