circuit-designoperational-amplifier
I'm trying to design a constant current LED driver and am totally confused!
This is the schematic i end up with:
simulate this circuit – Schematic created using CircuitLab
output current = Vref / R2?You have some boundary conditions: In your circuit the collector voltage is zero because the inverting input is a virtual ground. Also in the transdiode configuration, Ic=Ie, and Ve=Vout.
Use a reasonable approximation to the Ebers-Moll equation for currents that are greater than a uA. $$I_{c}\; =\; I_{s}\; e^{-\frac{qV_{E}}{kT}}$$ Is is emitter reverse saturation current. You solve for a variable in the exponent of an exponential by using its inverse, the natural log. $$\ln \left( \frac{I_{c}}{I_{s}} \right)\; =\; \frac{qV_{E}}{kT}$$ and solve for V $$V_{E}\; =\; -\frac{kT}{q}\; \ln \left( \frac{I_{c}}{I_{s}} \right)$$ This is V across the transistor junction and because the virtual ground at the inverting input is zero, this is V on the output, and is negative (inverted of course).
In your circuit, current into the virtual ground must equal current out, so current through the transistor is the same as current through the resistor. This means $$I_{c}\; =\; \frac{V_{in}}{R_{1}}$$ and substituting $$V_{E}\; =\; V_{o\; }=\; -\frac{kT}{q}\; \ln \left( \frac{V_{in}}{I_{s}R_{1}} \right)$$ kT/q has units of volts so for simplicity, replace with a scaling voltage in front. $$V_{o\; }=\; -V_{t}\; \ln \left( \frac{V_{in}}{I_{s}R_{1}} \right)$$
This is the first time I have used LaTex so I was a little distracted. Hope it makes sense. There are approximations and simplifications I can expand on.
Here is an application note circuit that may be useful. The power monitor chip is more economical than an analog multiplier and allows the load to be grounded, which is a big advantage in many applications.
As it says in the app note, the circuit can be scaled easily and the simple linear output stage could be replaced with a SMPS block.
The circuit controls the power to the load in parallel with the divider so it tails off a bit at high load resistances, but it's still not too shabby even at the 100mW output level.
Your circuit looks conceptually okay, concerns would include the input voltage range of the instrumentation amplifier and its common-mode rejection. Stability is the most likely thing to cause headaches in many of these circuits.
Best Answer
simulate this circuit – Schematic created using CircuitLab
Figure 1. The redrawn schematic. This shows the feedback arrangement more clearly.
R1 and C1 are creating a low-pass filter between the base and emitter to help prevent oscillations.
$$ f_{cut-off} = \frac {1}{2 \pi RC} $$
Yes. The voltage will rise on the output until V- = V+. This will occur when \$ I = \frac {V_{ref}}{R_2} \$.
The current will be affected. You need to reduce it anyway. See below.
simulate this circuit
Figure 2. An adjustable current source. Any pot in the 1k to 100k range should work fine.
Drop the reference voltage to 1 V (for easy maths) and you should get it to work.