Electrical – Critical Path for combinational block

digital-logicverilogvivado

I am trying to synthesize a combinational logic block in verilog using Xilinx Vivado. I am trying to reduce the number of luts and still try to find the critical path of the circuit.

Many solutions tell that the timing analysis is done from register to register. However if the output are made as registers the area of my design increases.

Is there a way to find the critical path of the behavioural design without using output registers?

Best Answer

How to constrain the paths without registers?

Yes, there is a way. Timing paths don't have to be from register to register. A port also can be a startpoint or endpoint. If your block is completely combinational, all paths will be from input ports to output ports.

The most important thing here is to define a virtual clock and input/output delays in an XDC file. Then you must add the file to the Vivado project.

create_clock -name VCLK -period 10.0 -waveform {0 5.0}

set_input_delay  1.0 -clock [get_clocks VCLK] [get_ports IN1]
set_output_delay 2.0 -clock [get_clocks VCLK] [get_ports OUT1]

The example above tells that IN1 signal arrives to the block 1ns after VCLK rises. In addition, OUT1 has to be set 2ns before VCLK rises. Since our clock period is 10ns, the path from IN1 to OUT1 has 7ns (10-1-2) to finish the operation.

How to see the critical path in Vivado?

Once the implementation is completed, click "Reports" at the bottom of Vivado GUI. Then click "Timing Summary Report" under "Route Design". As an alternative, you may also search blabla_timing_summary_routed.rpt file in the project directory.

This report shows the critical paths for all clock domains. Since you have only one clock domain, you should see something like below.

From Clock:  VCLK
  To Clock:  VCLK

Then find the section "Max Delay Paths". You will see the critical path below it.

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