Electrical – D Flip Flop design using multiplexer

flipflopsequential-logic

I was trying to implement a simple D Flip Flop using 2 multiplexers.

Are there any errors in design?

Do you have any other suggestions about design? Thanks.

Update:
As you'd recognise I've not implemented the clock signal yet.

I used this example when designing the circuit.

There are two latches. When C=0, Q holds its old value Q' follows the input D. When C=1 Q' holds its old value Q follows Q'.

Best Answer

The truth-table for a D-FF is

D Q | Q+1
0 0 | 0
0 1 | 0
1 0 | 1
1 0 | 1

So, your circuit does not work. At least my simulation tells me this

Qn gets high while Q is high also
Qn is not high when Q is low
Q is only high when D and C are high... as soon as C gets low, Q also is low - but it should hold the value

Edit 2: added inverters as suggested in comment

So corrected inverters a second time (sorry it was almost 2 o clock in the night).

I still see Outputs changing when clock is low, and Qn not being the inverse of Q

Still wrong... or?

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Electronic – OP-AMP Flip Flop start up predictability

Sure can. It's the 10k to V+. As the circuit powers up, assuming the set and reset lines are held at the same value, the - input to the op amp will reliably be held higher than the + input. During the early stages of the power-up cycle, while V+ and V- are low, the output transistors in the op amp output stage are not able to produce much current. As a result, the output is not able to override the pullup resistor before the output state is established, and the reset state is established.

And your paranoia is justified. If you cannot guarantee the condition of the set and reset inputs during power-up, you cannot guarantee that they will not override the pullup resistor. So a POR (power on reset) pulse or level is ALWAYS a good idea.

Verilog inital value for flip flop

You are using c as an active high reset, then setting the value to c rather than 1'b0. It is active high so c is always 1 when this code executes. The solution to this is the reset condition to 0 not c:

always @(posedge clk or posedge c) begin
  if (c) begin
    x <= 1'b0; //Reset Condition
  end else begin
    //x <= ...;
  end
end

Your code makes use of an initial and asynchronous reset. This does not really represent any type of hardware you have to choose one or the other, you can not have both.

The waveform in the question does not show the async reset being applied at the start of the simulation. you should apply it for at least 1 clock cycle and release it on the posedge of your clock.

Best Answer

Related Solutions

Electronic – OP-AMP Flip Flop start up predictability

Verilog inital value for flip flop

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