Electrical – DDR3 length-matching between signal groups

ddr3high speed

I currently dig into the design incorporating an application processor and one piece of DDR3 memory.
I already found out how the individual signal groups are formed and about the guidelines concerning trace length matching.

What I can not figure out without going quite deep :
1.)Why must the clock diffpair (and therefore the ADDR/CMD/CTRL groups) be longer than the DQ lines?

2.) Why isn't there a lower limit on the trace length of the DQ signals?

3.)Is the ODT sertting individual for each line or does the tuning process take one value for all the data lines?

Thanks a lot!

Best Answer

The minimum length of the DQ lines does not matter because you will just change how you terminate your lines. Depending on how many sockets you have will change the termination load. You need impedance matched boards for this reason. I haven't seen the more recent development guidelines, but board layouts are pretty much given to you.

The control groups are longer due to "cross talk", and this is why you have the WR_DATA_DELAY value in the control registers. You make the control lines as long as you need to, and then you add some time for the setup.