I'm a little confuse about this default assignment concept.
Normally, in order to avoid a latch, we should explicitly give a value to a signal in every case.
-- Assuming a is std_ulogic and b is std_ulogic_vector(3 downto 0) process(a, b) begin if a = '1' then b <= "1010"; else b <= "0101"; end if; end process;
But why in the following process, an else statement is not necessary.
process(clock, reset) begin if reset = '1' then b <= "0000"; elsif rising_edge(clock) then b <= b_next; -- Why don't we need an else statement here? end if; end process;
Can anyone help me out? Thanks!