Electronic – VHDL Assignment Statement

Depends on how you want to build your filter. The real questions are these: what sample rate do you need, and how long is your filter? If your sample rate is low, then you can get away with an FSM driven design that can use many clock cycles to produce each output sample. It's certainly a good idea to make the FSM as efficient as possible, though. No sense on wasting extra cycles doing nothing, though it may make sense to do some pipelining so you can run at a high clock speed and get timing closure more easily. If your sample rate is high, then you can't spare the clock cycles and will have to implement more parallelism, probably in the form of some sort of pipelining. If your sample rate is so high that you need to process multiple samples on each clock cycle, then you need to do some pretty careful pipelined design.

Flag state will be sampled on the next clock edge. In the synchronous design, all the conditions are (or must be) "prepared" before clock edge occurs, and when it occurs, circuit transitions to new state within very short timeframe. Thus in situations like yours circuit will see previously "prepared" condition, thus previous state of the flag. On the next clock edge new flag value will be "prepared", and it will be sampled.

You spend whole cycle to get the new propagated flag value; you may consider to trigger one process on rising edge, and another process on the falling edge, this way you will spend only half of the cycle.

Update (as per comments below): when designing circuits driven by both edges of the clock, you must pay close attention to the duty cycle of the clock, not just its period.