I am trying to analyse a discrete differential amplifier circuit by answering some question. I have done the analysis of the input stage, I would appreciate if I can get some feedback on my approach.
Here is my approach for the input stage
Here is the other part of the differential amplifier
Here are the calculations for the input stage
Best Answer
Your approach misses what's going on, and over-concentrates on minutiae. Basically you can't see the wood for the trees.
A better approach would be to say
a) assuming inputs are roughly at ground potential
b) then means roughly 24v is across R135 (ignore 0.7v in comparison to 24v), so about 200uA is flowing in R135
c) which for equal base voltages will split 100uA to each transistor.
That's enough accuracy for the bias conditions, any more polishing is superfluous, and shows you don't understand what is important.
Next, we have to figure out what the gain of this emitter coupled pair is. You haven't done that yet.
d) The input voltage, the difference between the base voltages, acts to drive a current through the effective emitter resistances. What are they? The slope of the base-emitter diode voltage for base current gives the effective resistance. As a rule of thumb, it's around 25ohms for a room temperature silicon diode at 1mA, and scales inversely with bias current. So with junctions conducting 100uA, and two in series, it's around 500 ohms.
e) That signal current flows through the collector resistor R117, with value 15k. Therefore the voltage gain of this stage is 15k/500, which is about 30x.
f) now you have to analyse the pair that's the 'other way up'. When you finally add the results together in the output stage, you'll find that the 'input voltage around 0v' assumption wasn't as necessary as first thought!
You'll notice I haven't used Vbe, but assumed it's small, and haven't used hFE, assumed it's big, at least compared to the calculated gain of 30x. Neither are needed to get the bias conditions and the gain well within the ballpark.