To answer your last question first. THe source is defined by what terminal you connect your bulk connection. So no, there is no difference in the S/D until that connection is made. However, different process technologies impose different connections. In a typical CMOS (now-a -days) the substrate is using <100> P-type. Which means that the bulk is always connected to ground for NMOS (NMOS transistors are built in P-type wells). The PMOS, (built in N-Wells) can have a "floating" bulk connection because the N-Well to P-substrate will be reverse biased. For a PWell in P-sub connection (NMOS) you can see there is a direct connection.
MOS transistor gates are capacitors, when there is a voltage imposed on the gate (lets only talk about NMOS here, PMOS is the inverse) say a +'ve voltage. Electrons are attracted to the other "side" of the capacitor plate (this happens to be the channel) to balance the charge. the channel has p-dopants in it which when the voltage is applied get ionized by the E-field. This is what establishes the channel. The positive potential at the surface drives the holes away from the surface, leaving it depleted. The charge that is in the channel that equates the gate charge is due to the uncovered acceptor atoms (p-dopants).
As the gate voltage increases, the substrate can be seen to move through three separate regimes. The first (at low E-Field levels) the substrate is enhanced there are lots of majority carriers (holes). As the voltage increases the substrate goes into depletion and finally as the voltage increases further the substrate inverts and the channel connects to the electron reservoirs at the S/D ends. These regimes also correspond to the regimes of operation (roughly) as sub-threshold, triode and active regimes of operation.
This also explains the capacitance change of the gate wrt Vgb or Vgs (for S=D). Below the threshold, the charge on the gate sees the acceptor atoms which are distributed in depth, so the opposite electrode to the capacitor looks almost "fuzzy" to it. i.e. the effective E-field can be thought to penetrate a little further, which decreases capacitance. Once the channel is established, all those electrons are gathered up close to the surface, the distance between plates is decreased and the capacitance is increased.
Yes, connecting the body to the source eliminates the body effect. However, this may or may not be possible in your intended fab process. If you want to connect an NMOS source to its body, and you expect the bodies of different NMOS transistors to be at different voltages, you need to have a process with P-Wells. If instead the process uses a P-type wafer with N-Wells for the PMOS transistors then you can't isolate the bodies of the NMOS transistors.
You may not care, but connecting the sources to the bodies can also significantly increase the capacitance on the source nodes. The well-to-well spacing requirement will also make your layout larger.
Best Answer
They are the same. And if the FET is deposited within a special implant, that implant called the tub or the well, then the tub and the well have become the same as body or bulk, and the substrate remains the larger structure upon which all the FETs of either polarity (some in wells for that reversed polarity) are implanted, as well as resistors and capacitors and diodes. And the bond-pads. And the special smiley-faces some layout people add.