Electrical – Error (209015): Can’t configure device. Expected JTAG ID code 0x02D010DD for device 2, but found JTAG ID code 0x00000000

cycloneerrorjtag

I'm having a weird problem where i cant upload my design to the DE0-NANO board, gives me the weird error message which is the title of this question.

Any other design uploads fine and I have done nothing different. Restarted the computer, rewrote the project, checked if the correct device is chosen and updated all the drivers, still doesn't upload.

Any suggestions?

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Problem solved. I named the .sdc file differently from the name of the project. Creating a new one with the right one solved the issue, not sure why, but here we are.

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Electronic – Arduino Diecimila (ATMEGA168) + JTAG ICE MKII Hell..Did I Fry the Chip

I believe I may have found a two part solution for my particular problem. I currently own an Arduino Diecimila (which has the ATMEGA168 with the problem) and also a new Arduino Nano 3.0. I went ahead and flashed the Arduino Nano with the ArduinoISP firmware. I then picked up 3 28 Pin ATMEGA328P DIP chips for $5.00 each at the local electronics store.

I used the ArduinoISP to flash one of the virgin chips with the Arduino Firmware using the above link with a crystal. I plan to now flash one of the other ATMEGA328Ps with the High Voltage Programmer firmware. This chip along with a bit of wiring on a breadboard should allow me to reset all of the fuses on the original ATMEGA168. Once that is done, I will be able to use the Arduino Nano to reprogram the chip.

Since the ATMEGA328Ps only cost $5 each, my end goal is to setup one 328 as an Arduino ISP programmer, setup the 168 as a HV Programmer, keep one 328 chip in my current Arduino Diecimila (upgrade!!), and I'll have one left over for whatever. I can then either switch chips on the Diecimila or build out a real board for the ISP and HV Programmer boards.

I still have not tested the JTAG ICE MKII yet with a logic/oscilloscope. Not sure if it is the root of the problem or not. I will address this issue after I build the HV Programmer.

I will report back on the success/failure of the HV Programmer. I just need to go get a few more 1K resistors to pull it off. Anyone ever tried the HV Programmer? Any other suggestions? If nothing else, hope this helps someone.

Electronic – Readying a New Design, would appreciate som feedback

When I review schematics/PCB during my day job, for a design like this, I would spend about 8 to 16 hours going over it. Clearly I cannot do that here. Further, I cannot give you a lesson in EE for each thing that is wrong in the design. And to make things worse, EE.SE is not really suited for a back-and-forth dialog that is normally required for a review like this. So here's what we'll do. I'll do a quick review of the design and put the issues that I spot in this answer. You read that, do some studying on your own, and if you still don't understand then you need to post a new question (not a comment on this answer). Here goes:

You need some EMI filtering on the +3.3v to the center tap of the Ethernet transformers. Some sort of ferrite bead + cap(s).
You need ESD protection diodes on the Ethernet signals to U4.
10 pF decoupling cap on X2 is astonishingly small. Use 0.1 uF.
Ethernet termination resistors, R42-45, must be at least 0805's to handle the wattage required. I can't tell what size you are using.
Something doesn't look right with the Ethernet TX CLK signal. I don't think you should have it connected to three chips (Oscillator, Phy, and MAC). Double check that in the Phy/Mac reference designs.
Put a 0.1 uF cap on the "input" side of your ferrite beads.
The note "crystal oscillator needs to be 12 mm away from the phy" is a HUGE red flag to me. It makes me think that something is not right, but I don't know what. If this were a normal design review I would grill you over this.
You should filter or buffer reset signals that go over connectors (like SHIELD_RESET). This is a huge way for an ESD event, even 6+ feet away, to cause the PCB to reset.
You should have a 0.1 uF decoupling cap(s) at every connector to reduce the AC signal return path for signals on the connector.
It doesn't look like you have enough input caps on the DC power input. I could be wrong, however, since I can't read your schematics that well (stupid web-app).
You might need more caps on the output of your voltage regulators. I didn't check, however, because I don't have time to read the datasheets.
It is hard to really judge the PCB layout without looking at the design in the CAD software (Altium). But I see enough issues that the whole design needs to be scrutinized before being send out.
Vias need to be spread apart so they don't cause slots in the power/gnd planes.
Additional gnd planes on the top and bottom layers is not adding much to the design. It is worth it to just remove those.
Do you have proper signal termination on the MII signals between the MAC and Phy?
Have you verified that the PCB layer stackup is correct for the trace impedance you want and the signal termination that you have>
You have signals crossing voids in adjacent power/gnd planes. This is a HUGE no-no.
Your signal GND plane and your chassis-gnd planes overlap. Never, ever do this. (Disclaimer: I could be looking at the plots wrong.)

So there you go. Good luck!

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Electronic – Arduino Diecimila (ATMEGA168) + JTAG ICE MKII Hell..Did I Fry the Chip

Electronic – Readying a New Design, would appreciate som feedback

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