Sir,
Whenever i simulate my vhdl code of 4 bit counter in Xilinx vivado 2015.2, i get the error message like following.
ERROR: [VRFC 10-724] found '0' definitions of operator "+", cannot determine exact overloaded matching definition for "+"
My vhdl code is
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity my_count is
Port ( clk : in STD_LOGIC;
clr : in STD_LOGIC;
y : out STD_LOGIC_VECTOR (3 downto 0));
end my_count;
architecture Behavioral of my_count is
begin
process(clk,clr)
variable temp: std_logic_vector(3 downto 0):="0000";
begin
if(clr='1') then
temp := "0000";
elsif(clk='1' and clk'event) then
temp := temp + 1;
end if;
y <= temp;
end process;
end Behavioral;
test bench is
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity my_count_tb is
-- Port ( );
end my_count_tb;
architecture Behavioral of my_count_tb is
component my_count
port(clk,clr: in std_logic;
y: out std_logic_vector(3 downto 0));
end component;
signal clr,clk: std_logic;
signal y: std_logic_vector(3 downto 0);
begin
process
begin
clk <=not clk after 5ns;
end process;
end Behavioral;
please help me to solve this error
Best Answer
Use the type system instead of fighting it.
Any time you see an uncomfortable double type conversion, especially to another type and immediately back again, like
that is fighting the type system, and probably points to a more or less serious mistake in the design.
Instead, think about this:
You want to count - so your data is some form of number, not just a bag of bits.
What range do you want to count? That's not clear from your question, so I'll guess 0 to 15, eliminating negative numbers, covering the 4 bits of output data.
There are 2 obvious choices :
You are already using the correct
numeric_std
library for the latter.Now there will be a suitable
"+"
operator visible.What's missing so far is a connection to the output port
y
.If you are forced by ridiculous coding standards or a huge existing project to keep all ports
std_logic_vector
you'll need a type conversion.If you are allowed to fix a broken design, consider what
y
means in the larger context : if it's an unsigned number such as a memory address, use the right type in the port declaration, then the simplesty <= temp;
is the correct approach.