Electrical – Generate clock jitter in a testbench

PLL is just a frequncy multiplier, output frequency static relative accuracy is just the same as your crystal e.g.
\$3\times (8\,\text{MHZ}+1\,\text{ppm})=8.000008\,\text{MHz} \times 3= 24.000024\,\text{MHz} = 24\,\text{MHz}+1\,\text{ppm}\$.

Output jitter is depends pretty much on PLL closed-loop bandwidth and power spectral density of timebase oscillator jitter but, long story short, PLL will anyway remove components above its closed-loop bandwidth and hence reduce -or at least do not increase- input jitter

Is there any possibility that you can change your FPGA design some so that the clock for the memory comes out on pads at the periphery of the BGA pin field? If so you open up the possibility of getting a much better differential routing of the clock at the FPGA end.

You should also re-evaluate the pair of vias showing in your layout at the memory end of the diff pair. The via placement and/or routing there is not balanced.

Finally you should look closely at what the diff traces are routed over and next to. It looks like you may have an nearby copper pour that could have edge fringe coupling to one of the diff pair conductors. Ideally this clock and all the other memory control signals as a set would be routed directly over a GND plane with no plane split crossings or parallel plane edges nearby.