Electrical – Generated clock constraints in vivado

fpgaverilogvivadoxilinx

I created my own clock since I need a 2Mhz clock and the clock generator IP wont let me go bellow 6Mhz. I created a clock divider module.

module clock_divider#(parameter HALF_CYCLE_COUNT = 128, COUNT_BITS = 8)
(
    input clk_in,
    output reg clk_out = 1'b0
);

    reg [COUNT_BITS - 1:0] counter = 1'b0;
    always @(posedge clk_in) begin
        if(counter == HALF_CYCLE_COUNT - 1) begin
            counter <= 0;
            clk_out = ~clk_out;
        end else counter <= counter + 1;
    end
endmodule

Here is my top level module.

module audio_visualizer
(
    input clk,
    input m_data,
    output m_clk,
    output reg m_lr = 1'b1
);

    wire pdm_clk;
    clock_divider#(.HALF_CYCLE_COUNT(100), .COUNT_BITS(7)) pdm_clk_div(clk, pdm_clk);
    assign m_clk = pdm_clk;

    wire [7:0] sample;
    wire sample_changed;
    sampler s(pdm_clk, m_data, 1'b0, sample, sample_changed);

    ila_0 i(clk, sample, sample_changed, pdm_clk);
endmodule

I want to declare a constraint so that vivado knows the frequency of pdm_clk. Here is what I have right now for clocking constraints.

set_property -dict { PACKAGE_PIN E3    IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L12P_T1_MRCC_35 Sch=clk100mhz
create_clock -add -name clk -period 10.00 -waveform {0 5} [get_ports {clk}];
create_generated_clock -name pdm_clk -source [get_ports clk] -divide_by 50 [get_ports pdm_clk]

I keep getting this error.

[Vivado 12-1387] No valid object(s) found for create_generated_clock constraint with option '-objects [get_ports pdm_clk]'. ["/home/chase/vivado-workspace/Sound/Sound.srcs/constrs_1/imports/Desktop/Nexys4DDR_Master.xdc":9]

I am not sure how to tell vivado what the output of the generated clock is. I have also tried [get_pins audio_visualizer/pdm_clk].

Best Answer

The problem is that pdm_clk isn't a port, it's a wire, and so won't be found by the get_ports search.

What you should instead do, is target the actual register driving the signal. You can do this with something like (haven't checked):

create_generated_clock ... {pdm_clk_div|clk_out}

Where in this case clk_out is the name of the register inside the ```pdm_clk_div` instance which is driving the clock net.

If the above doesn't work, you can try something like [get_pins {pdm_clk_div|clk_out}] or [get_registers {pdm_clk_div|clk_out}]

As a side note, if you are generating your own clocks, you should also include a BUFG primitive on the output so that the clock can be promoted to the global clock network. This will avoid excessive skew warnings later on during fitting.

However I agree with @johnnymopo's comment that the best approach is to use the original clock to drive your registers and then use the clock divider to generate a clock enable. Instead of generated clock constraints in this case you may instead require multicycle paths to declared if there are any timing issues.

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