According to your circuit, the 3v supply is connected directly to your ADC - forget about all the transistors and loads - 3V and 0V goes to the ADC.
Then, according to your measurements, the 3v supply is "much lower voltage than expected". So, you have the ADC telling you the reading is low and the meter telling you the same - what on earth makes you think the voltage is 3v?
I reckon the CR123A battery is "drooping" under load conditions.
Don't get bogged down in irrelevant details about line sizes, CPU architectures, etc. The key question is, what conditions would cause a fully-associative cache to replace a line when a direct-mapped cache would not?
Take a trivial example: A pair of caches that contain just two lines each, and three addresses, A, B and C, that do not fall into the same lines in memory. But let's assume that B and C map to the same line in the direct-mapped cache.
Now, take the addressing sequence A, B, C, A, B, C, A, ...
The fully-associative cache will take a miss on every access, since it always replaces the oldest entry with the new entry.
However, the direct-mapped cache will load A just once, and then only suffer misses on B and C, since neither of those will replace A.
Best Answer
Some devices do indeed have multiple enables, some have a mix of high and low. This is partly done to make the device more convenient for use and, in some cases I am fairly sure, were added to use up all the pins on the package.
It is common to use them to divide up the functionality when using them for address decoding.
Looking at your circuit above, you could double up that circuit to have a read decode and a write decode. In which case one would have the /E line attached to whatever /Write_Enable line comes from the micro, while the other would have the active high E pin connected to /Write Enable.
For a decoder, you can also use them as additional address lines, or to clock, synchronize, the output.