Electrical – How to transform the code for a read-write register to a read only register in Verilog

readregisterverilog

I have the code for read write register here

module read_write(
input             clk     ,
input             rst_n   ,
input      [31:0] data_in , //data to be written
input             rw      , //rw=1->write to data_out; otherwise, read from data_out
output reg [31:0] data_out 
);



always @(posedge clk or negedge rst_n) begin
if(~rst_n)
  data_out<=0;
else begin
  if (rw)               //write to data_out
    data_out<=data_in;
end
end
endmodule

How can I read data from a register? I am a bit confused, if I don't write the data to the register, how can I read something from the register?

Best Answer

To read its content at the given address...

I suspect your code has been reduced a bit too much, it is not looking at all like a CPU interface. This might be a school assignment so I only provide an outline of the code. (Which, by the way, has not been syntax checked)

...
input [7:0] read_only;
...
reg [7:0] write_only;
reg [7:0] read_write;


always @(posedge clk or negedge reset_n)
begin
   if (!reset_n)
   begin // set reset value of registers
      ...
   end
   else // clocked
   begin
      if (cpu_write)
         case (cpu_address[2:0])
         3'b000 : write_only <= cpu_write_data;
         3'b001 : read_write <= cpu_write_data;
         endcase
      else
      if (cpu_read)
         case (cpu_address[2:0])
         3'b001 : cpu_read_data <= read_write;
         3'b010 : cpu_read_data <= read_only;
         endcase
   end // clocked
end // always

Related Solutions

Electronic – Verilog asynchronous reads of regs – and design question

Your code simulates two multiplexers. These are actually asynchronous components. The fact that Verilog requires data1_temp and data2_temp to be declared as reg's is a quirk of Verilog syntax and your choice of coding style, and doesn't mean these signals would be the outputs of storage elements in a physical implementation.

If you want to capture these values in actual registers, you need to add those explicitly:

reg [7:0] data1, data2;
always @(posedge someclock) begin
    data1 <= data1_tmp;
    data2 <= data2_tmp;
end

But I would like to know what this mini register file would be made of in hardware. Particularly, the 4x8 bit array consisting of k0,k1,k2,k3.

You haven't shown how these variables are assigned, so it's not possible to say how they are implemented. As your code showed, just declaring them as reg doesn't guarantee they are implemented with actual storage elements. If you assign them inside a block that begins always @(posedge clk) then very likely they are flip-flops, but there are ways you could code them that would make them synthesize differently.

I thought when it came to registers and arrays like this, you need a clock to read out data, like RAM?

You need a clock to update a (physical) register. You can read it out at any time. For example:

wire [8:0] sum;
assign sum = k0 + k1;

is perfectly valid code. sum will change whenever any of its inputs changes. If k0 and k1 are the outputs of flip-flops, their values will only change when there is a clock edge.

For another example, you could equally well describe your multiplexers with code like this:

reg [7:0] k0, k1, k2, k3;
wire [7:0] data1_tmp;
reg [1:0] reg1;
// k<n> and reg1 are assigned elsewhere.
assign data1_tmp = (reg1 == 0) ? k0 :
                   (reg1 == 1) ? k1 :
                   (reg1 == 2) ? k2 : k3;

how do I read from this tag_array and do the comparison all within the same clock cycle?

Let me repeat a key point for emphasis: You need to use a clock to assign a new value to a register (an actual hardware register or group of flip-flops). It's output is available at any time.

RAMs are different and how you access the contents of a RAM will depend on details of the type of RAM you use.

I got confused because frankly I don't know enough about memory hardware and how that's possible.

Another key strategy: When you are learning digital logic, I recommend you learn about the physical hardware first, and then work out or study how to simulate it in HDL second. So first, learn what a physical flip-flop is, then learn the standard Verilog methods of describing a flip-flop. Especially if you are trying to write HDL for synthesis, trying to write good code before you learn the capabilities of the underlying hardware will lead you down a lot of dead-end paths.

Help with $readmemb

Surely you need some thing more along the lines of :

#20 {X,Y,Z} = testvectors[vectornum];

However $readmemb is meant for initialising memories. Reading the file line by line using scanf would seem more appropriate here. This would also be similar syntax used to write the output to a file.

integer data_in_file; //file handler
integer i;
integer r_in; //file handler

//input data
logic signed [31:0] dat1_in;
logic signed [31:0] dat2_in;
logic signed [31:0] dat3_in;

initial begin
data_in_file  = $fopen("data.in", "r");
for(i=0; (i<500) && (!$feof(data_in_file)); i=i+1) begin
   #20ns;
   //Expecting 3 decimal numbers
   r_in  = $fscanf(data_in_file, "%d %d %d\n", dat1_in, dat2_in, dat3_in);
end

To write a file:

integer data_file_out;
logic signed [31:0] a; //Data driven some where else

initial begin
  data_file_out= $fopen("test", "w");
  //place write inside loop
  $fwrite(file, "%b", a); //Wrte a as Binary number 
end

Best Answer

Related Solutions

Electronic – Verilog asynchronous reads of regs – and design question

Help with $readmemb

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