footprint
I know IPC-7351C is not released and probably won't be for… forever? The draft version of IPC-7351C differ from what's out there in the wild in many ways. For example, the draft uses a bar instead of a dot to indicate pin 1.
Has anyone seen any PCB with IPC-7351C land patterns in the wild (any photo, maybe)? Does the new silk screen cause any confusion at PCB assembly manufacturers?
Generally speaking, there could be as many footprints as you need depending on the criteria set to be satisfied in each possible (working) case.
Below is an example of a hypothetical SMD resistor's footprints prepared in relation with the target board manufacturing/fabrication process: hypothetically you desire the first if you plan to design a pcb that will be fabricated in a small number with next manual assembling, ect...
Returning to IPC, at least IPC-7351 defines three distinction criterions which could be combined very arbitrarily depending again on your design goals:
Performance Classification Three general endproduct classes have been established to reflect progressive increases in sophistication, functional performance requirements and testing/inspection frequency... :
Class 1 General Electronic Products ...
Class 2 Dedicated Service Electronic ...
Class 3 High Reliability Electronic Products ...
Producibility Levels When appropriate this standard will provide three design producibility levels of features, tolerances, measurements, assembly, testing... :
Level A General Design Producibility – Preferred
Level B Moderate Design Producibility – Standard
Level C High Design Producibility – Reduced
Land Pattern Determination ... Three land pattern geometry variations are supplied for each of the device families... :
Density Level A: Maximum (Most) Land Protrusion ...
Density Level B: Median (Nominal) Land Protrusion ...
Density Level C: Minimum (Least) Land Protrusion ...
At the most principal part of the description in this standard:
It is the responsibility of the user to verify the SMT land patterns used for achieving an undisturbed mounting process, including testing and an ensured reliability for the product stress conditions in use.
It is in IPC-7351B. I have the original document, not the "B" version, and the information is in Section 3, Design Requirements. The dimensions aren't given directly; instead, there are suggested allowances and tolerances depending on the part size, lead shape, etc. For example, here is a table suggesting how much extra space to give around the component leads:
As you can imagine, it's not easy to use this document, especially when all you want are land patterns :)
I highly recommend using Library Expert. It packages all of the IPC-7351 recommendations together. The Lite version is free, and it creates IPC-7351-compliant footprints for a bunch of PCB tools, including Altium, OrCAD, Eagle, etc...
You can tell it which Density Level to uses ("Most", "Nominal", and "Least"). This refers to how much the land patterns will protrude from the actual point of connection.
Please see this earlier answer for more info on Density Levels.
Good luck.
Best Answer
One example is a card I recently design.
As you can see U1 follows this convention which is capture in IPC-7351C
Likewise here is a render of a card I have in fabrication+assembly (2more weeks and you would see a picture and not a render)
As you can see, U2, U8, U7,U3 ... follow this convention.