Electrical – k-bit signed multiplier

verilog

I am asked to design a 4-bit signed multiplier using only combinational circuits. Verilog code.

I have designed a 4 bit multipler:

The Half adder module

module HA(sout,cout,a,b);   //for Half adder mux
 output sout,cout;
 input a,b;
 assign sout=a^b;
 assign cout=(a&b);
endmodule

The Full adder module

module FA(sout,cout,a,b,cin);   // for full adder mux
 output sout,cout;
 input a,b,cin;
 assign sout=(a^b^cin);
 assign cout=((a&b)|(a&cin)|(b&cin));
endmodule

The multiply module

module multiply4bits(product,inp1,inp2);
 output [7:0]product;
 input [3:0]inp1;
 input [3:0]inp2;
 assign product[0]=(inp1[0]&inp2[0]);

 wire x1,x2,x3,x4,x5,x6,x7,x8,x9,x10,x11,x12,x13,x14,x15,x16,x17; //wire range started from [1:17]

 HA HA1(product[1],x1,(inp1[1]&inp2[0]),(inp1[0]&inp2[1]));
 FA FA1(x2,x3,inp1[1]&inp2[1],(inp1[0]&inp2[2]),x1);
 FA FA2(x4,x5,(inp1[1]&inp2[2]),(inp1[0]&inp2[3]),x3);
 HA HA2(x6,x7,(inp1[1]&inp2[3]),x5);
 HA HA3(product[2],x15,x2,(inp1[2]&inp2[0]));
 FA FA5(x14,x16,x4,(inp1[2]&inp2[1]),x15);
 FA FA4(x13,x17,x6,(inp1[2]&inp2[2]),x16);
 FA FA3(x9,x8,x7,(inp1[2]&inp2[3]),x17);
 HA HA4(product[3],x12,x14,(inp1[3]&inp2[0]));
 FA FA8(product[4],x11,x13,(inp1[3]&inp2[1]),x12);
 FA FA7(product[5],x10,x9,(inp1[3]&inp2[2]),x11);
 FA FA6(product[6],product[7],x8,(inp1[3]&inp2[3]),x10);
endmodule

I think that is right, but now I need to extend it and add 2's complement at the end?

Best Answer

A simple approach would be to convert both factors to sign/magnitude representation. Be sure to use 1 bit for sign and 4 for magnitude to avoid overflow for the value -8. XOR the signs and apply that to the result. This can be done in another verilog module, wrapping your multiply4bits-module.

This combinatorial function will probably be optimized to something completely different when you look at the synthesis result. There are far better approaches when you want to optimize for resources or delay. Look at this excellent paper by Ray Andraka for an overview.

In your case, Booth's algorithm would be a good approach.

Related Solutions

Electronic – Synthesis of a multiplier design

I presume that you are synthesising for an FPGA or CPLD. The simulator will successfully simulate many language constructs which are technically valid Verilog, but are very hard to translate to real programmable logic hardware.

I can't synthesise your block myself as I don't have the part_prod_gen1, count_one and shift modules available, but the problems I can see from reading the code are:

Using posedge and negedge always@ blocks for signals other than clock and reset lines often isn't synthesisable (see this answer). I think that using shift registers (explicitly or with a signal_old register) is a much more reliable approach than testing for posedge of count[0].

Register array qq elements are assigned in multiple separate processed (always blocks). This is not synthesisable as the process blocks run in parallel and the register flip-flop cannot be set from two different sources. You can rectify this by combining much of the code into a single sequential process (which is ugly and harder to debug) or using intermediate wires which are combined together in a single process. See this answer for a similar problem.

genvar j, i,  k, m;
// ... other code
//load the partial products
generate
  for (j=1; j<=16; j=j+1)
  begin: loop1
    always @ (posedge clk)
    begin
      if (!reset) begin
      // ... qq assignments
      end
    end
  end
endgenerate

/* should be */

genvar i,  k, m;
integer j; // j as integer not genvar
// ... other code
//load the partial products
//generate // comment out or remove
always @ (posedge clk)
begin
  for (j=1; j<=16; j=j+1) // <- for-loop inside always block
  begin: loop1
    if (!reset) begin
    // ... qq assignments
    end
  end
end
//endgenerate // comment out or remove

Electronic – Creating a verilog code for 4-bit multiplier using lookup table

There are two different ways the term "lookup table" are used in FPGA design that might be confusing you.

First, the main building block of combinatorial logic in an FPGA is called a lookup table, but usually abbreviated as LUT. This is just a small RAM element that takes 4 or 5 or 6 inputs (depending on which type of FPGA you have) and uses that to select a bit from memory to be output.

Second, more generally a lookup table is just logic that takes inputs and has a defined output for every combination of those inputs, just like a logic table you'd use for paper-and-pencil design. Since a hardware LUT in an FPGA isn't big enough to implement a 4-bit adder, this is probably the kind of lookup table that's meant in your problem.

In Verilog, a lookup table is usually implemented with a case statement. For example, to implement a 2-input XOR gate with a lookup table you might write,

reg out;
wire [1:0] in;
always @(in)
case(in)
    2'b00 : out = 0;
    2'b01 : out = 1;
    2'b10 : out = 1;
    2'b11 : out = 0;
endcase

For your 4-input multiplier, you will probably want to use bit concatenation to form the input bits:

wire [3:0] A;
wire [3:0] B;
...
case ({A, B})
    ...
endcase

And your case statement will have 256 lines in it.

Best Answer

Related Solutions

Electronic – Synthesis of a multiplier design

Electronic – Creating a verilog code for 4-bit multiplier using lookup table

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