Electrical – lpddr2 interface differences between different memory controllers


The way LPDDR2 connections are done with CA bus is different between these two processors. I thought since LPDDR2 is a JEDEC standard, these schematics should be interfacing with the same lines from their respective memory controllers. How would I figure out what lines from my processor to connect on the CA bus?

The main differences are in the CA[3:6] lines. This is what I feel like should be standard and having a hard time interfacing with my chip which provides no guidelines.
Device 2
Device 1:

Best Answer

The bits involved are all address bits in the first command phase for MRW (which simply therefore changes what logical address is used for a given physical address), although these are also column bits in the bank commands during both first and second phases.

These bits are also used in writing the mode register (data for mode register), so certain bits are out of order, but as that is a driver dependency, it can be catered for.

The truth table is in JESD209

CA Truth Table