digital-logiclogic-gateslogic-levelnoise
The noise margin is defined as:
Noise Margin High = VOH – VIH
Noise Margin Low = VIL – VOL
Is the noise margin calculated the same way for schmitt and non-schmitt buffers? If so then why?
This question is within context of input output buffers of ASICs.
This is what the article says: -
By using current signals and low impedance data acquisition devices, industrial applications benefit from better noise immunity and longer transmission cable lengths.
The article also says, in relation to devices that produce voltage signals, that: -
These devices are sensitive to the noise induced by nearby motors, conveyor belts, and radio transmissions.
Basically it's true but there are some caveats. Consider the noise induced by motors and for this, I reckon induction motors are a likely culprit. They produce magnetic fields that can induce an interfering voltage in a cable whatever the signalling type is.
When voltage signalling is used, the interfering voltage is additive to the signal just like batteries in series are additive. This adds an error.
When current signalling is used AND, providing the induced voltage is not several volts, the current flowing in the cable (due to the signal) remains exactly that current and no voltage interference is seen at the receiving end - this is because of the high-compliance of the 4-20mA current source: -
simulate this circuit – Schematic created using CircuitLab
Hopefully you can see that for a high-compliance current source, interfering voltages that arise in series with the current loop have little effect.
Where does this start to go wrong: -
(1) The compliant current source may need a few volts across it to maintain performance and if the series voltage causes the minimum voltage to drop-below this point there will be glitching introduced onto the signal.
(2) At high frequencies, the compliance will change from theoretically infinite resistance to more like a small value capacitor (due to the transistors and chips in the device). This will allow high frequency interferers to circulate a current through the 100 ohm receiver (R1).
If low frequency signalling is used (with appropriate low-pass filtering at the receive end) HF interference can largely be avoided and it is advised to use screened/shielded twisted pair cable.
High energy E-field interference (as opposed to magnetic interference) tends to be seen as a voltage in parallel with the two wires and this also directly impinges on R1 so shielding and filtering is needed.
The driver is the output of one logic gate (or flip-flop or other logic devices), and the receiver is the input of another logic gate.
In any system using digital logic, you will have many logic circuits interconnected, with each interconnection having a driver and one or more receivers.
In that description, the driver and receiver are not parts of a single device.
Best Answer
The noise margin calculation is the same for all types of inputs.
When you have a constant voltage level (either high or low), the noise margin prevents noise from changing the logic level seen at the input.
When the signal is switching (high→low or low→high) and near the actual threshold, noise could make the voltage level seen at the input cross the threshold multiple times. A Schmitt trigger has two threshold levels (hysteresis), which prevents these oscillations. (See What is a Schmitt Trigger and its application exactly?)