Electrical – Overflow detection for the given case

digital-logic

Two 2's complement numbers having sign bits x and y are added and sign bit of result is z.Then occurence of overflow is indicated by which boolean function?
I believed that overflow occurs when the XOR of the sum and carry is 1 ,there is overflow,else no overflow.Keeping this in mind,I came up with the following truth table:

X Y Z Overflow

0 0 0 0

0 0 1 1

0 1 0 1

0 1 1 0

1 0 0 1

1 0 1 0

1 1 0 0

1 1 1 1

Is this table correct?

Best Answer

When can an overflow happen?

Adding a positive and a negative number yields a number in between them (lower border inclusive), thus no overflow is possible.
Adding two positive numbers will always result in a positive number.
Adding two negative numbers will always result in a negative number.

-> An overflow is only possible when both summands share the same sign.

Can an overflow wrap around more than once?

In a n-bit 2's complement number,

the maximum number is \$2^{n-1}-1\$. Adding two of them yields: $$2\cdot(2^{n-1}-1)=2^n-2=-2$$
the minimum number is \$-2^{n-1}\$. Again adding two of them: $$2\cdot(-2^{n-1})=-2^n=0$$

-> In case of an overflow the result will be always negative for positive summands and positive for negative summands.

Conclusion

An overflow has happened if, and only if, both summands have the same sign and the result has the other sign.

Related Solutions

Electronic – hardware implementation of division algorithm

Flowcharts are often not a very precise way of indicating what hardware is doing, since flowcharts often imply the existence of a single execution process, whereas hardware often does many overlapping and simultaneous operations.

The portions of the diagram circled in red seem a bit odd. It seems odd to latch A with the value after subtracting B, and then re-add B. More natural would simply be to not bother latching the lower part of the subtraction result. I think the flowchart might be clearer if "named values" were separated into "registers" and "values", and each step either computed values or registers. Thus, for example, one could have something like (assuming 16-bit registers)

C:T[15..0] = (A[14..0]:Q[15]) + ~B-1
if (C or A[15])
  A[15..0] = (A[14..0]:Q[15])
  Q[15..1] = Q[14..0]
  Q[0] = 1
Else
  A[15..0] = T[15..0]
  Q[15..1] = Q[14..0]
  Q[0] = 0
Endif

Every step that updates registers would represent a system clock. Events that merely compute values would not require a clock edge, but would be processed asynchronously.

Electronic – Theory for 3-bit full adder and calculations with un-/signed integers

Yes, it can be either. It will work with unsigned 3-bit numbers. It will also work with 2s complement signed numbers. You'll need to do a bit of study, but the thing to remember with 2s complement is that a 0 sign bit means positive, and a 1 means negative.