Electrical – real to std_logic_vector in VHDL

vhdl

I have trouble understanding conversion between different data types in VHDL and needed help with conversion to `STD_LOGIC_VECTOR' type in VHDL.

I want the code below to be synthesized such that it can be used on real hardware.

For now i have the code setup as follows

signal   VREF  : real := 65536/3.3;
constant SIG   : real := 2.33;
signal TEMP    : unsigned(15 downto 0);

signal WORD_A : STD_LOGIC_VECTOR(23 downto 0) ;
signal SIG_A  : STD_LOGIC_VECTOR(15 downto 0);

BEGIN

TEMP <= to_unsigned(VREF,16)*to_unsigned(SIG,16);
SIG_A <= STD_LOGIC_VECTOR(TEMP);
WORD_A <= "00110000" & SIG_A;

I used the following libraries : IEEE_NUMERIC_STD.ALL, IEEE.MATH.REAL

I get the following error
ERROR: [VRFC 10-1471] type error near VREF ; current type real; expected type natural

Any inputs is appreciated

Thanks

Best Answer

real is not synthesisable in FPGA. You can use:

library ieee

package ieee_fixed_pkg.all

Related Solutions

Electronic – std_logic_vector to unsigned conversion throwing incompatible error

Problem here is that abus(i) is of type std_logic and no vector. Inserting a '0' helps to create a vector that can be casted to unsigned:

sum := sum + unsigned( '0' & abus(i) );

Here's a helpful numeric_std cheat sheet: http://www.lothar-miller.de/s9y/categories/16-Numeric_Std

Electronic – How to specify “don’t care” signals in VHDL

I will leave it to an LRM expert to provide a more detailed answer, but in short, your approach should be valid - I ran a quick test with a recent version of Quartus, and it handles '-' like it's supposed to - the logic generated is reduced as expected when the output is defaulted to '-' ('X' works too, by the way). More on the approaches you listed:

Not assigning the signal isn't really an option for your example, of course, if you don't want latches. If it's a clocked process, you're slightly better off, but you'll still get enables where you might not need them. Maybe I'm missing your intent here.
'-', as previously noted, is probably the best option, for both semantic and practical reasons.
Depends on what you mean by "undefined". 'X' is technically "unknown". 'U' is for uninitialized signals, which ModelSim displays as "X" for hex representations. 'X' does seem to work, though, as I noted above.

Another alternative would be to do the optimization yourself and remove one case from being tested explicitly:

if instruction(15 downto 8) = "11111001" then
  write_data <= std_ulogic_vector(resize(signed(instruction(7 downto 4)), 16));
else
  write_data <= std_ulogic_vector(resize(signed(instruction(7 downto 0)), 16));
end if;

This has significant disadvantages (mostly related to code clarity), though, and I would probably opt for a more ideal solution.

Incidentally, '-' is also commonly used with std_match(), which I would consider using for your decoding, e.g.:

if std_match(instruction(15 downto 8), "1100----") then

Though at that point, you're probably better off just using case?.

Best Answer

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Electronic – std_logic_vector to unsigned conversion throwing incompatible error

Electronic – How to specify “don’t care” signals in VHDL

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