Electronic – the standard way to represent fixed point numbers in VHDL

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Is there a native type in VHDL language similar to std_logic_vector that allows one to create a signed or unsigned fixed point number for given length of fractional and whole parts? If so, can it be synthesized?

How does one see fixed point quantities in wave window in test bench? Does one need to create a variable of type real and then use it to represent the fixed point quantity after manual conversion?

Are there functions in VHDL 2008 for conversion to and from fixed point and VHDL real type?

Best Answer

If You'd like to implement fixed point arithmetics in synthesizable VHDL you have two ways:

  1. Do It Yourself. It's rather hard method, but it may depend on quantity and complexity of equations You want to implement. Generally every "variable" should have two parts (integral and fractional) made of std_logic_vectors. Of course You have to implement basic (addition, subtraction etc.) mathematical operations.
  2. Just download and use package fixed_pkg, it implements signed and unsigned fixed point types and all basic math - more here.

But first of all - do You really need fixed (or floating) point types? Most math could be done on std_logic_vector, just like we do in microcontrollers using int types.

EDIT:

Unfortunately, link to the libraries inside pdf guide from above link is dead. Someone delete the files. But it shouldn't be a problem - currently all ieee_proposed libraries are moved to standard VHDL2008, so just change the used standard in the properties of Your project.

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