Electronic – How to assign a hexadecimal value to integer type in VHDL

modelsimtypecastvhdl

ModelSim is unable to compile this in VHDL:

constant mem_size_bytes: integer := x"FFFFFFFF";

It says:

Bit string literal found where non-array type std.STANDARD.INTEGER was expected.

Similarly for;

if address< x"3FFFFF" then

it says

Operator "<" is ambiguous

I keep running into this problem. How in the world am I supposed to use hexadecimal numbers in VHDL with integer types like integer, natural and positive? Its just that specifying something hexadecimal is more convinient at times than having to use the calculator to determine what something is in radix-10. I had hoped that the tool will automatically know what the literal means since it is preceded by x which marks it as hexadecimal numeric quantity!!!

So, when assigning literals to constants or when using literals in comparison operator how does one qualify the literal? In other word for a literal constant value like "1010", how do explicitly tell the compiler if this is a string or std_logic_vector or unsigned or signed?

Best Answer

VHDL supports arithmetic values but it has to know if they are signed or unsigned. I recommend using the numeric_std library to support these types.

VHDL is strongly typed. For your first question, I would use:

EDIT: I have erased a prior more complex form and used this simpler one after Brian Dummond's comment

constant mem_size   : integer := x"FFFF_FFFF";

The second, supposing address is an std_logic_vector, has to be written:

if unsigned(address) < x"3FFFFF" then
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