I wanted to make use of a single port RAM to be a single clock FIFO in verilog for an asic project , due to some constraints i can not use the dual port RAM. My confusion is when I have to perform read and write simultaneously, I thought about using a faster clock and give 1 cycle for read another cycle for write, but that option is not preferable, in the context of my project. There is the idea of making a system with priority for read however I am not sure how to manage the write request. If I give priority to read I might lose some write requests as well.
Thanks
Best Answer
You need to define your requirements more carefully.
How many reads can occur on contiguous clock cycles?
How many writes can occur on contiguous clock cycles?
If the answer to both is "just one", then all you need is a simple aribter. Do the read when requested, and if a write happens at the same time, hold it in a register until the next clock cycle — which is guaranteed to be available.
If reads or writes can occur in larger "bursts", then things get quite a bit more complicated, and you might as well bite the bullet and put in a true dual-port memory, or clock your single-port memory at twice the speed.