I'm very new to digital design (my background is software). I'm trying to make use of some block RAM on a Xilinx FPGA, and I want to know what the usual methods are for setting up the RAM control signals w.r.t. the clock.
I currently have a single clock used by all of my design. The RAM can perform a read/write every rising edge, and I want to use it at that rate. Of course, the control signals need to be set some time before the rising edge of the clock. I imagine there are a few ways to do this:
- Set the signals on the falling edge of the clock.
- Set the signals on the rising edge. The synthesis tool is clever enough to know what I want, knows the required setup time, and takes care of everything.
- Set the signals on the rising edge. The synthesis tool isn't clever enough, but I can do funny things with timing constraints to get the signals set up early enough.
- Use two clocks slightly out of phase, set the signals on the rising edge of the leading clock.
- Some other approaches?
Which of these are possible, which are actually good or usually used, and are there any advantages or disadvantages to help choose between them?
Edit: I'm using plain VHDL for reasons of portability, and not using Xilinx-specific CoreGen or primitives. I'm following Xilinx documenation though, and writing the VHDL in such a way as to let the tools infer the correct RAM type ("RAM HDL Coding Guidelines in UG687 if anyone is interested). The tools seem to be doing this correctly.
Best Answer
You don't need to use the other edge, or phase shift the clock.
Just set the data up on the rising edge, and then the next rising edge will clock it in to the memory (as per option 2).
Running static timing analysis will tell you of any hold/setup violations. But if you add proper waveform constraints to your clock (i.e. frequency, duty), the fitter will do its best to meet the timing requirements.
This is the fundamental basis of synchronous design. Every register clocks on the same edge at the same time, so theoretically the data from the last cycle at any register input will always be loaded in on the current cycle. This is achieved primarily using low-skew H-tree clock architectures - where the distance from the clock source to any register is pretty much the same length with the same delays - so theoretically every register should clock at the same time.
The data will take a bit longer to arrive (as it has DFF propagation delay and routing delay) before it gets to the next register, meaning that the input of a register will change at some point after the clock edge that set it up (and hopefully before the edge that is supposed to load it).