Electronic – How to route a LVDS clock from FPGA input to output

Using VHDL, How is it possible to receive a pair of LVDS signals (say external clock) on the FPGA and route them to another pairs of pins to go out, without any modification?

I have tried IBUFDS and OBUFDS with an intermediate single-ended signal in between but all I get at the output is a rising edge, not a clock. I also tried to put ODDR in between but I got the same.

I am using Xilinx 7 series FPGA (on Zynq) and it has LVDS pins. The VHDL code and the constraint file is like this:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VComponents.all;

entity fanout is
  Port ( CLK_IN_P  : in  STD_LOGIC;
         CLK_IN_N  : in  STD_LOGIC;
         CLK_OUT_P : out STD_LOGIC;
         CLK_OUT_N : out STD_LOGIC;
         LD0       : out STD_LOGIC);
end Fanout;

architecture data_flow of fanout is
  signal clk_lvcmos : STD_LOGIC;
begin

  -- LVDS input to internal single
  CLK_IBUFDS : IBUFDS
  generic map(
    IOSTANDARD => "DEFAULT"
  )
  port map(
    I  => CLK_IN_P,
    IB => CLK_IN_N,
    O  => clk_lvcmos
  );

  -- Internal single to LVDS output  
  CLK_OBUFDS : OBUFDS
  generic map(
    IOSTANDARD => "DEFAULT"
  )
  port map(
    O  => CLK_OUT_P,
    OB => CLK_OUT_N,
    I  => clk_lvcmos
  );

end data_flow;

and the UCF file is:

# Input clock differential pair
NET CLK_IN_N LOC = C20  | IOSTANDARD=LVDS_25 | DIFF_TERM = TRUE;  # "FMC-LA18_CC_N"
NET CLK_IN_P LOC = D20  | IOSTANDARD=LVDS_25 | DIFF_TERM = TRUE;  # "FMC-LA18_CC_P"

# Output clock differential pair
NET CLK_OUT_N    LOC = G21  | IOSTANDARD=LVDS_25;  # "FMC-LA20_N"
NET CLK_OUT_P    LOC = G20  | IOSTANDARD=LVDS_25;  # "FMC-LA20_P"