Electrical – System Verilog code syntax error

digital-logiclogic-gatessystem-verilogverilog

I wrote the following code:

module mul3 (
    input logic[1:0] d
);
mul3_op[0]=d[0];
endmodule;

But when I run it using Modelsim I get the following messages:

Error: (vlog-13069) mul3.sv(21): near "[": syntax error, unexpected
'['.

Error: mul3.sv(21): (vlog-13205) Syntax error found in the
scope following 'mul3_op'. Is there a missing '::'?

Please note that line 21 is actually the last line before endmodule in the code above. Any idea of what is wrong?

Best Answer

You missed assign keyword for that concurrent statement -

assign mul3_op[0] = d [0] ;

Related Solutions

Electronic – “is not declared” error in Verilog

You need to give the instance a name (see below)

It also looks like you may be trying to declare it in an always block, this won't work. Declare it outside any blocks (e.g. at the top of the module)

Also, using the "connection by name" (or named association) method of instantiation rather than "connection by order" (or positional association) is less prone to accidental errors from getting the order wrong, especially with modules with many ports.

So the instantiation for connection by name would be

encoder8to3 enc_instance (.A(LL), .B(x), .F(FAULT));

With this method it could be written like this and still be correctly connected:

encoder8to3 enc_instance (.A(LL), .F(FAULT), .B(x));

Whereas using:

encoder8to3 enc_instance (LL, FAULT, x);

would connect B to FAULT and F to x.

Here's a reasonable pdf on modules and instantiating them. I agree good Verilog tutorials are quite thin on the ground (compared to something like C) so starting out can be a bit bewildering.
If you can find a copy at a reasonable price, I do highly recommend the Pong Chu book "FPGA Prototyping with Verilog Examples" I mentioned in my answer to your other question, as well as the focus on synthesis I mentioned, it goes through everything you need to start writing decent code, and is very clear and concise.
There is also a google mailing list for Verilog you might find of use, and fpga4fun has some good tutorials and a forum. And of course there is here :-)

EDIT - about where to declare the module:

The instantiation only connects the ports together, so where you declare it (outside a block) doesn't matter.
If you want to do something with this module inside the always block use some intermediate logic. Create a couple of registers, use the always block to manipulate them as desired, then tie these to the instantiated module ports (in the instantiation).

The way you have it at the moment, the instantiated module can be seen as in parallel with your module rather than inside it, as it just connects directly to the inputs and output of the module. Have a look at the RTL schematic to see what is being generated by the code (under synthesis in the design tab)

How to resolve this Syntax error

Wires need blocking assignments (=), not non-blocking (<=). You can define it this way:

wire In3 = Data[3], In2 = Data[2], In1 = Data[1], In0 = Data[0];

Example here

More commonly you will see the declaration and assignments as separate statements. The two are functionally equivalent

wire In3, In2, In1, In0;
assign {In3, In2, In1, In0} = Data;

Best Answer

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Electronic – “is not declared” error in Verilog

How to resolve this Syntax error

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