Electrical – SystemVerilog import statement outside module definition

system-verilog

What does an import statement outside of a module (|class|package) definition mean?

Does it apply to entire file?

Is it even legal? I don't see it in IEEE Std 1800™-2012.

It seems to be tolerated by ncsim (15.10-s008) – this compiles/runs w/o error:

package myPackage;
  integer  count  = 0;
endpackage//myPackage

import myPackage::*;

module a;
    initial begin
        myPackage::count++;
        #1;
        $display("%0d: %m: myPackage::count=%0d", $time, myPackage::count);
        $display("%0d: %m:            count=%0d", $time,            count);
    end//initial 
endmodule//a

module b;
    import myPackage::*;
    initial begin
        count++;
        #1;
        $display("%0d: %m:            count=%0d", $time,            count);
        $display("%0d: %m: myPackage::count=%0d", $time, myPackage::count);
        myPackage::count++;
        #1;
        $display("%0d: %m:            count=%0d", $time,            count);
        $display("%0d: %m: myPackage::count=%0d", $time, myPackage::count);
    end//initial
endmodule//b

module test_package;
    a a();
    a b();
    b c();
    b d();
endmodule//test_package

Best Answer

It applies to the compilation unit, which is the scope outside a module / interface / package. That is normally a single file on your compilation command line ( and everything it includes, which is the same as C/C++) or it could be everything on the current compilation step. The default is tool dependent.

See section 3.12.1 Compilation units in the 1800-2012 LRM.

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