Electrical – A question about instantiating a module with a parameter in systemverilog

system-verilog

I'm now writing a testbench. In my testbench, I want to read the length of a text file and pass it to another module while instantiating. The idea is like this:

module TB();
integer text_len;

ABC #(.text_len(text_len)) ABC_1(//some input/output arguments here);

task read_text(output integer text_len);
//read text file and get the text length
endtask

initial 
begin
read_text(text_len);
end

endmodule

When I compile it using Questasim, it keeps saying the expression for a parameter actual associated with the parameter name text_len for the module instance ABC_1 must be constant.
Does anyone know how to deal with it?

Best Answer

The problem is module instantiation happens at code elaboration before the simulation of any initial blocks. So you cannot use a variable to override a module parameter.

What you can do is parse the file externally to Verilog and either create a `define definition that you compile your source code with, or Questa allows parameter overrides through the command line (look for the vopt -g/-G switches in the user manual)

The defines.vh file would look like 

`define TEXT_LEN 5

And your module file would look like

module TB();
`include "defines.vh"

ABC #(.text_len(`TEXT_LEN)) ABC_1(//some input/output arguments here);
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