circuit-designcmosdelaydigital-logicmosfet
With regards to the image above, I wanted to know what is the importance of Fan Out of 4 (FO4) for optimum design and what improvements does it incur over designs that are either higher or lower than fan out of 4?
Also, with respect to the picture, what are the issues seen in circuits 1 ,2 and 4 as compared to circuit 3 with N=3, F=4, TP=15?
N = number of stages
F = fan out
TP = propagation delay
If I understand correctly your aim is to have falling slope of inverters appear later than rising slope? If so, if it is available reduce W/L ratio of NMOS transistor and increase W/L ratio of PMOS transistor.
Capacitances on the output are seen both by NMOS and PMOS transistors.
What you've actually made between your signal line & your AD8676 in the second diagram is a "pi attenuator."
While a pi attenuator could actually be used quite well in this instance, I think yours has the wrong resistor values.
Here's a link to a calculator made specifically for making impedance-matched pi attenuator circuits like that: Pi Attenuator Calculator
using that calculator, if your op-amp had an input impedance of 50ohms, the following would work:
simulate this circuit – Schematic created using CircuitLab
Since, however, the input of the OA is closer to 1Mohm than 50ohm, you'll probably want to do a little checking on "Impedance Matching Pi Networks" if you need to avoid reflections on the incoming signal cable.
Or, if we stop over-complicating things on ourselves, using the fact that the op-amp's input can be considered infinite-impedance, compared to the 50-ohm required load, you could use this even simpler circuit:
Best Answer
The fanout-4 inverters are simply a design metrics, a benchmark in silicon manufacturing for characterization of a typical delay. It is used to compare efficiency of different manufacturing nodes. There is no special significance, just an accepted metrics.