How do I obtain the falling delay driving by signal A:
NMOS W/L=1/.35 PMOS W/L=2/.35 Resistor-NMOS= 1/2 and PMOS5 Kohms.micro Cgate=Cdif=4/3fF/microm Cmetal-ground=100fF Cmetal-metal=39fF Rmetal 800 ohms
1.-When B is not switching
2,-When B is switching simultaneously in the same direction than A
3.-When B is switching simultaneously opposite to A
If I understand correctly your aim is to have falling slope of inverters appear later than rising slope? If so, if it is available reduce W/L ratio of NMOS transistor and increase W/L ratio of PMOS transistor.
Capacitances on the output are seen both by NMOS and PMOS transistors.