Electronic – How to design a CMOS buffer with exact same delay of a CMOS inverter

cmosdigital-logic

Everyone knows that a CMOS inverter is simply a PMOS connected to an NMOS. There are situations in asynchronous design that we need to compensate for the inverter propagation delay in a parallel signal running along side of the other signal. In that case I can see that designers add a buffer in gate level schematics.

But I need to implement that buffer by myself using CMOS cell libraries and it seems to me the most rational approach is just to put two inverters in series which inverts the signal twice hence acts like a buffer. But it seems to me that the propagation delay also will be doubled.

How one can have a buffer with EXACT same propagation delay of an inverter?

Best Answer

A common solution is to have to two path as shown in the figure below. The first path is a inverter chain to buffer the signal, or it could be a single inverter if the load is low. The second path is almost identical to first, but one inverter is replaced by a transmission gate like structure.

Using a simulator is should be possible to equalize the delays.

(Please note that the bulk should be tied to ground and vdd for the NMOS and PMOS, respectively. It's not drawn correctly.)

schematic

^{simulate this circuit – Schematic created using CircuitLab}

Best Answer

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