Electronic – CMOS inverter with feedback

This is a homework problem, right?

First of all check whether transistor conduct.

• PMOS conducts when \$V_{SG}>|V_T|\$.
• NMOS conducts when \$V_{GS}>V_T\$.

If any of them is in cut-off, then the solution is very simple, right? If both are not in cut-off then we proceed.

You got two separate transistors. This means that you can write two separate current equations. This complicates by the fact that MOSFETs have different equations for "linear" and "saturation" modes of operation. There are four possible combinations for modes of PMOS-NMOS: linear-linear, linear-saturation, saturation-linear, saturation-saturation. You'll need to guess here and check if your guess works - if it doesn't, then you'll get unsolvable equations. In this case you simply check the other combinations. However, just by inspection of the circuit you may be able to eliminate some of the possibilities.

What the unknowns are in these equations? Hint: there are up to four of them (currents, voltages).

You can't solve for four unknowns having just two equations. Too bad. But if you can relate some of the unknowns to each other, you may be able to reduce their number. Try to see what constraints are imposed by the schematic (current relations, voltage relations, ...).

The combination of modes which provides you with a solution for \$V_d\$ is the answer (together with the solution itself).

Diverger - I think some confusion can arise because there are always two different ways to explain the functioning of oscillator circuits (models). Normally, we discriminate between two-pole and four-pole oscillators - however, it is important to know that this is nothing else than a different way to describe the oscillation principle.

a) Two-pole oscillators can be described using the concept of negative resistances, and

b) Four-pole oscillators are described using the classical feedback loop (in conjunction with Barkhausen`s criterion).

For most oscillator topologies it is not a problem to explain the working principle using both models (after suitable redrawing and/or change of the common ground). As mentioned in both application notes, the basis for the shown oscillator is the Pierce topology, which very often is considered as a two-pole type (but not necessarily).

• Regarding your question "gain vs. transconductance": The CMOS inverter has a relatively large output resistance so that it makes sense to use the corresponding transconductance gm for gain calculation. In this respect, of course the connected load is important (in both notes there is an external resistor Rext, which is NOT shown in your drawings!). Thus: voltage gain=gm*load resistance.

• Regarding the role of Rf: This resistor is necessary to fix the wanted DC operational point (bias point) of the analog CMOS amplifier. In addition, this resistor attenuates the resonant loop and, thus, influences the total loop gain. For this reason there is a recommended/preferred range of values which ensures safe start of oscillations - and this range somewhat depends on the oscillation frequency because the total resistance of the crystal feedback loop depends on frequencies.