Electronic – Level shifting in HV CMOS processes

cmoslevel-shiftingtransistorsvlsi

I'm working on a project for which custom ICs are being designed by another person on the project. The process being used is a mixed voltage CMOS process which uses a \$1.8\mathrm{V}/5\mathrm{V}\$ logic level along with a \$60\mathrm{V}\$ high voltage capability. Essentially the circuits being designed involve high voltage output drivers which must be driven from the low voltage logic. Naturally this requires level shifting.

The high voltage transistors in the process are designed for \$60\mathrm{V}\$, but as with most transistors, this is only the \$V_{ds}\$ rating. The \$V_{gs}\$ rating is naturally much lower – in this case only \$5\mathrm{V}\$.

The restricted gate voltage clearly makes level shifting difficult – somehow a \$5\mathrm{V}\$ control signal for the low side needs to be shifted up by \$55\mathrm{V}\$ in order to control the high side transistor of a half-bridge. However this is not a simple task as the gate voltages are limited.

The IC guys who are working on this basically have two solutions. Firstly, use a resistor for the high side rather than a PMOS which as you can imagine would consume an awful lot of power as the resistance needs to be low enough to achieve fast rise times (\$20\mathrm{ns}\$) into a fairly large (\$10\mathrm{pF}\$) capacitive load. Secondly, use a resistive divider driven by a low side NMOS to produce the \$60\mathrm{V}/55\mathrm{V}\$ logic level for a high side PMOS – but again this would use a lot of power as the gate of the PMOS is a ~\$2\mathrm{pF}\$.


Not being an IC designer myself, I'm leaving them to do their job, but I suppose it's just been bugging me. I can't help pondering over the problem and thinking there must be a better way, but I can't think of one.

I'm curious as to whether there are typical ways of achieving this sort of level shifting with limited components?

Effectively the only components are the PMOS/NMOS above, resistors, diodes, and I think 5.5V Zener diodes too. There are capacitors in the process to but as I recall they are low voltage, so couldn't be used in structures I've seen that can level shift pulses over a large voltage using capacitors for isolation.

I suppose what is bugging me the most is it seems odd that IC fabs offer high voltage processes with seemingly no 'nice' way of linking the PMOS and NMOS transistor together to form push-pull drivers.

Best Answer

Most technologies are limited to VGS < 10 V, or 5 V in more modern ones, and need circuits like this. High voltage level shifters are needed in high voltage DC/DC converters and similar circuits.

The general approach is to create a rail that is ~ 5 V below the HV supply and use this to limit the VGS of the high side FETs. You also don't drive the 10 pF load directly -- buffers (also powered from the HV-5 supply) minimize the load on the level shifter portion itself.

Care needs to one taken in these circuits to ensure that the HV devices don't get damaged; that the outputs are controlled when the supplies are starting up, and that speed is maintained.