You need to give the instance a name (see below)
It also looks like you may be trying to declare it in an always block, this won't work. Declare it outside any blocks (e.g. at the top of the module)
Also, using the "connection by name" (or named association) method of instantiation rather than "connection by order" (or positional association) is less prone to accidental errors from getting the order wrong, especially with modules with many ports.
So the instantiation for connection by name would be
encoder8to3 enc_instance (.A(LL), .B(x), .F(FAULT));
With this method it could be written like this and still be correctly connected:
encoder8to3 enc_instance (.A(LL), .F(FAULT), .B(x));
Whereas using:
encoder8to3 enc_instance (LL, FAULT, x);
would connect B to FAULT and F to x.
Here's a reasonable pdf on modules and instantiating them. I agree good Verilog tutorials are quite thin on the ground (compared to something like C) so starting out can be a bit bewildering.
If you can find a copy at a reasonable price, I do highly recommend the Pong Chu book "FPGA Prototyping with Verilog Examples" I mentioned in my answer to your other question, as well as the focus on synthesis I mentioned, it goes through everything you need to start writing decent code, and is very clear and concise.
There is also a google mailing list for Verilog you might find of use, and fpga4fun has some good tutorials and a forum. And of course there is here :-)
EDIT - about where to declare the module:
The instantiation only connects the ports together, so where you declare it (outside a block) doesn't matter.
If you want to do something with this module inside the always block use some intermediate logic. Create a couple of registers, use the always block to manipulate them as desired, then tie these to the instantiated module ports (in the instantiation).
The way you have it at the moment, the instantiated module can be seen as in parallel with your module rather than inside it, as it just connects directly to the inputs and output of the module. Have a look at the RTL schematic to see what is being generated by the code (under synthesis in the design tab)
It does, however you need to make temp
a signed value and do not specify the range when using the arithmetic shift. Specifying the range in the arithmetic shift casts a unsigned value.
reg signed [31:0] temp;
always @* begin
temp = 32'hfff00fff;
result[31:0] = temp >>> shamt[4:0];
end
Alternatively, you can cased it as signed with $signed
reg [31:0] temp;
always @* begin
temp = 32'hfff00fff;
result[31:0] = $signed(temp[31:0]) >>> shamt[4:0];
end
Working example(s) here
Best Answer
It is important to remember that with Verilog you are describing hardware, not writing software. Modules are instances of hardware. They can't be called and they don't return a value.
You can't instantiate a module conditionally within an if statements (*), and you definitely can't instantiate them within procedural blocks. If you consider what such a statement would describe it becomes clear as to why not. With a module instantiation within an if statement you are basically saying:
FPGAs can't work like that. All hardware is described and fixed at synthesis.
Instead what you need to do is instantiate your hardware (in this case right shift module) not within the if statement or procedural block. Connect the output of that module to a wire. Now your hardware is always present, regardless of the control signals. So how do you make use of it conditionally?
This is quite simple. Within the if statement you can use your wire. If a condition is met assign the wire to whatever signal you are controlling. Otherwise assign some other signal.
The reason this now works is because rather than trying to infer transient hardware, you are now inferring a simple multiplexer. The inputs to the multiplexer are the
module_output_wire
andsomething_else
, the select signal issome_condition
, and the output of the multiplexer issome_signal
. The hardware always exists, but you don't always need to use the output value.As an alternative, you could make your right shift code a function. A function in Verilog can be called in the way you show on the commented out line in your code. In the case of the function you are inferring hardware that is always there and the output of the hardware is a wire (the return value of the function) which you can then use in an always block.
(*) With the exception of in Verilog 2001 Generate statements, but in that case the condition is known at compile time, it doesn't depend on the value of a signal.