Electrical – Verilog RAM module with Register File & Testbench

fpgaramverilog

I am designing a RAM module with testbench in Verilog. It is suppose to access a register file (.dat) in the testbench and run it through an ALU module. There are 4 modules (memory.v, alu.v, toplevel.v and testbench.v).

My problem is that when I run the ModelSIM I am not getting the expected results.

`timescale 1ns/1ps

module testbench_lab3_reg();

reg clk;            
reg [4:0] Read_address;
reg [4:0] Write_address;
reg read_en; 
reg write_en;
wire [15:0] DataOut;
reg [15:0] memory [0:15];

assign DataOut = (read_en) ? memory[Read_address] : memory[Write_address];

lab3_reg dut(.clk(clk), .Read_address(Read_address), .Write_address(Write_address), .read_en(read_en), .write_en(write_en), .DataOut(DataOut));

always
begin
    clk = 1; #10; clk = 0; #10;
end

initial begin
$readmemb("memfile.dat", memory);

Read_address = 5'b00000; Write_address = 5'b01001; read_en = 1;  write_en = 0; #20;
Read_address = 5'b00000; Write_address = 5'b01001; read_en = 0;  write_en = 1; #20;

Read_address = 5'b00001; Write_address = 5'b01010; read_en = 1;  write_en = 0; #20;
Read_address = 5'b00001; Write_address = 5'b01010; read_en = 0;  write_en = 1; #20;

Read_address = 5'b00010; Write_address = 5'b01011; read_en = 1;  write_en = 0; #20;
Read_address = 5'b00010; Write_address = 5'b01011; read_en = 0;  write_en = 1; #20;

Read_address = 5'b00011; Write_address = 5'b01100; read_en = 1;  write_en = 0; #20;
Read_address = 5'b00011; Write_address = 5'b01100; read_en = 0;  write_en = 1; #20;

Read_address = 5'b00100; Write_address = 5'b01101; read_en = 1;  write_en = 0; #20;
Read_address = 5'b00100; Write_address = 5'b01101; read_en = 0;  write_en = 1; #20;

Read_address = 5'b01001; Write_address = 5'b00000; read_en = 1;  write_en = 0; #20;
Read_address = 5'b01010; Write_address = 5'b00000; read_en = 1;  write_en = 0; #20;
Read_address = 5'b01011; Write_address = 5'b00000; read_en = 1;  write_en = 0; #20;
Read_address = 5'b01100; Write_address = 5'b00000; read_en = 1;  write_en = 0; #20;
Read_address = 5'b01101; Write_address = 5'b00000; read_en = 1;  write_en = 0; #20;

$stop; 

end
endmodule

I know my ALU works because I tested it using a MegaWizard generated RAM. The following is my ram module:

module memory(
input clk,
 input [15:0] write_data,
input [4:0] raddress,
input [4:0] waddress,
input read_enable,
input write_enable,
 output [15:0] read_data);
reg [15:0] memory [0:15];
 reg [15:0] data_out;

assign read_data = data_out;

always @(posedge clk) 
 begin
    if (write_enable) 
        memory[waddress] <= write_data;
      if (read_enable)
            data_out <= memory[raddress];
end

endmodule

The following is my top level module, which instantiates the ALU and the RAM:

module lab3_reg(
            input clk,
            input [4:0] Read_address,
            input [4:0] Write_address,
            input read_en,
            input write_en,
            output [15:0] DataOut
            );


wire zero;
wire signed [3:0] y;
alu inst1(DataOut [12:9], DataOut [8:5], DataOut [15:13], y, zero);

wire signed [15:0] y_signed;
assign y_signed = y;

wire [15:0] data;
assign data = DataOut;
memory inst2(clk, y_signed, Read_address, Write_address, read_en, write_en, data);

endmodule

I'm pretty sure the problem is with my testbench, but I've been racking my brains over this, so any help would be awesome.

memfile.dat

0100000111100000
1100000111100000
1111111000000000
0001111111100000
0010000111100000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000

Best Answer

May be I misunderstand something, but where is inputs for your ALU module? So I think, the first problem in your structure is, in the case you haven't inputs for ALU you write into the memory unknown values (U or Z, what you have on ALU output) when write_en is active;

The second problem is in the module lab3_reg you have incorrect assignment in line assign data = DataOut;, it should be assign DataOut = data; because data is output of internal module you have "X" on the port (multiple drivers);

And last problem is in the tesbench testbench_lab3_reg module, there you also have bad assignment assign DataOut = (read_en) ? memory[Read_address] : memory[Write_address]; in this line. DataOut is output of your top module, but in the line you assign another value, in the case you also will get "X" on the wire.

Try to fix the mistakes in the assignments logic to correct and then I think your module will work well.

P.S. By the way, what do you want to get by the follow assignment assign DataOut = (read_en) ? memory[Read_address] : memory[Write_address]; when DataOut is output? If you want to use bidirectional bus you should declare it like inout in modules.

Related Solutions

Electronic – wrong with this attempt at an SDR RAM in Verilog

I got this working, with one specific change although to be honest some other edits may have helped too.

I thought about how drive_data is set up using combinatorial logic, but the outdata register is clocked. Confirmed with behavioural sim, this means that stale data is driven out during the first part of a read cycle, before the address is latched.

I "fixed" this by changing the always block that sets outdata to do so on every clock, meaning the right data gets in there during the setup phase while address is valid on the bus, before the OE strobe comes along.

I also refactored my memory bus handling into a submodule (inverting the control signals).

module emif(
    input clk,
    input [1:0] addr,
    inout [15:0] data,
    input ce,           // note these signals are active high
    input we,           // (opposite to the PCB signals)
    input oe
    );

wire drive_data;
reg [15:0] mem [0:3];
reg [15:0] em_outdata;

assign drive_data = ce && oe && !we;
assign data = drive_data ? em_outdata : 16'bz;

// writes data to small mem
always @ (posedge clk)
begin
    if (ce && we) begin
        mem[addr] <= data;
    end
end

// reads data from small mem
always @ (posedge clk)
begin
    em_outdata <= mem[addr];
end

endmodule

Electronic – Verilog asynchronous reads of regs – and design question

Your code simulates two multiplexers. These are actually asynchronous components. The fact that Verilog requires data1_temp and data2_temp to be declared as reg's is a quirk of Verilog syntax and your choice of coding style, and doesn't mean these signals would be the outputs of storage elements in a physical implementation.

If you want to capture these values in actual registers, you need to add those explicitly:

reg [7:0] data1, data2;
always @(posedge someclock) begin
    data1 <= data1_tmp;
    data2 <= data2_tmp;
end

But I would like to know what this mini register file would be made of in hardware. Particularly, the 4x8 bit array consisting of k0,k1,k2,k3.

You haven't shown how these variables are assigned, so it's not possible to say how they are implemented. As your code showed, just declaring them as reg doesn't guarantee they are implemented with actual storage elements. If you assign them inside a block that begins always @(posedge clk) then very likely they are flip-flops, but there are ways you could code them that would make them synthesize differently.

I thought when it came to registers and arrays like this, you need a clock to read out data, like RAM?

You need a clock to update a (physical) register. You can read it out at any time. For example:

wire [8:0] sum;
assign sum = k0 + k1;

is perfectly valid code. sum will change whenever any of its inputs changes. If k0 and k1 are the outputs of flip-flops, their values will only change when there is a clock edge.

For another example, you could equally well describe your multiplexers with code like this:

reg [7:0] k0, k1, k2, k3;
wire [7:0] data1_tmp;
reg [1:0] reg1;
// k<n> and reg1 are assigned elsewhere.
assign data1_tmp = (reg1 == 0) ? k0 :
                   (reg1 == 1) ? k1 :
                   (reg1 == 2) ? k2 : k3;

how do I read from this tag_array and do the comparison all within the same clock cycle?

Let me repeat a key point for emphasis: You need to use a clock to assign a new value to a register (an actual hardware register or group of flip-flops). It's output is available at any time.

RAMs are different and how you access the contents of a RAM will depend on details of the type of RAM you use.

I got confused because frankly I don't know enough about memory hardware and how that's possible.

Another key strategy: When you are learning digital logic, I recommend you learn about the physical hardware first, and then work out or study how to simulate it in HDL second. So first, learn what a physical flip-flop is, then learn the standard Verilog methods of describing a flip-flop. Especially if you are trying to write HDL for synthesis, trying to write good code before you learn the capabilities of the underlying hardware will lead you down a lot of dead-end paths.

Best Answer

Related Solutions

Electronic – wrong with this attempt at an SDR RAM in Verilog

Electronic – Verilog asynchronous reads of regs – and design question

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