Electrical – vhdl – convert a signal to integer

fpgasignalvhdl

I have looked around on SE but couldn t find anything that worked properly for me.

I am looking for a way to convert a 4 bit signal_vector to an integer. However I do calculations on signals as well. This means I need the library called

use IEEE.std_logic_arith.all

This is (the condensed version of) what I have so far:

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
USE ieee.numeric_std.ALL;
use IEEE.std_logic_unsigned.all;

    signal counter: std_logic_vector(3 downto 0);

    counter<=counter + "0001";
                ...

       if ((to_integer(counter)) < (to_integer("0100"))) then

      -- do something

      end if;

this gives me the following error: Identifier "unsigned" is not directly visible.

Best Answer

Please do not use the ieee.std_logic_arith library. It is outdated and makes problems when combining with others.

You can convert your signal as following:

library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.ALL;

signal counter: std_logic_vector(4 downto 0);

counter<=std_logic_vector(unsigned(counter) + 1);
            ...

   if (unsigned(counter) < to_unsigned(4, counter'length)) then

  -- do something

  end if;

If you plan to use a signal as a number most of the time, try to use type unsigned or signed if possible. You can always convert it to a std_logic_vector if needed.

Source: http://www.bitweenie.com/listings/vhdl-type-conversion/ Source: http://www.bitweenie.com/listings/vhdl-type-conversion/

EDIT:

I made a complete codesample that compiles and simulates in Vivado (should also work in modelsim):

library ieee;
use ieee.STD_LOGIC_1164.ALL;
use ieee.numeric_std.ALL;


entity test is
--  Port ( );
end test;

architecture Behavioral of test is
   signal counter: std_logic_vector(4 downto 0) := (others => '0');
   signal bigger: std_logic;
   signal clk: std_logic;
begin

make_clk: process
begin
    clk <= '0';
    wait for 2 ns;
    clk <= '1';
    wait for 2 ns;
end process;

test: process(clk)
begin
    if rising_edge(clk) then
        counter<=std_logic_vector(unsigned(counter) + 1);
        if (unsigned(counter) < to_unsigned(4, counter'length)) then
            --do something
            bigger <= '0';
        else
            bigger <= '1';
        end if;
    end if;
end process test;
end Behavioral;
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