Electrical – VHDL nested generate statements: how to refer to label

vhdlxilinx

I have this code that attaches a label to components instantiated inside a for...generate statement. So far everything works fine:

outer: for index in 17 downto 0 generate
attribute RLOC of EX_do1: label is "X0Y" & integer'image(index / 4);
begin
  EX_do1: FDC port map( ... );
end generate;

However, I want the attribute only on instances 0..15. So I tried this:

outer: for index in 17 downto 0 generate
begin

  inner: if index < 16 generate
    attribute RLOC of EX_do1: label is "X0Y" & integer'image(index / 4);
  begin end generate;

  EX_do1: FDC port map( ... );
end generate;

Now I'm getting the error message <EX_do1> is not declared. I tried moving inner before the begin of the outer statement, but same result. How can I refer to the flipflop?

I assume it would be possible by pulling the component initialization into the if-block and repeating it again in an if-not-block, but I am trying to avoid redundant code.

Best Answer

I found an old comp.lang.vhdl post that led me to the FAQ.

Section 4.2.3 seems to suggest that you can use one or more additional for loops to assign your attributes, by referring to the instances of your FDCs using the syntax outer(index).EX_do1.

I'm not set up to verify this myself — let me know whether or not it's helpful.

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