I'm not able to write vhdl syntax. But for the exam we must be able to read and interpret it.
The essence of the code is
process{
if(start)
c := 0;
end if;
if ( c )
...
c := false;
else
c:= true;
....
end if;
}
Assuming that c=1 (is a variable) in the beginning. I'm having difficulties interpreting what happens here
Best Answer
Since the statements are inside a
process
they will execute sequentially just like software.http://www.doulos.com/knowhow/vhdl_designers_guide/components_vs_processes/
If you have
use ieee.std_logic_1164.all;
andstart
is set totrue
or1
elsewhere in the code, thenif ( c )
would evaluate tofalse
theelse
branch would be executed. Thenc
will be set tofalse
and will retain that value until the next time this process executes (or some other process or combinatorial statement changes it).If you don't have
use ieee.std_logic_1164.all;
the behavior is dependent on the compiler/synthesizer.http://www.eda.org/vfv/hm/1153.html
There is a lot of code missing so I'm making a lot of assumptions here but hopefully you get the basic meaning.