VHDL programming issues…newbie

I'm trying to write a state machine in VHDL that will scan a 4×4 keypad. I want keyP set to 0 at the start and after a Reset. I also want the Col to be set to "1111" at the start and after a Reset.

As I'm not fully versed in VHDL programming I'm sure it's just a stupid syntax error.
The error I get is:

Error (10818): Can't infer register for "Col[0]" at Lab_7_Keypad.vhd(39) because it does not hold its value outside the clock edge

and the same for Col[1] Col[2] Col[3] and for keyP as well.

Here's my code for the start of it all. Can someone give me an idea where I've gone wrong?

ENTITY Lab_7_Keypad IS
PORT(
nReset          :   IN  STD_LOGIC;
clk             :   IN  STD_LOGIC;
row             :   IN  STD_LOGIC_VECTOR (3 downto 0);
Col             :   OUT STD_LOGIC_VECTOR (3 downto 0);
data            :   OUT STD_LOGIC_VECTOR (3 downto 0);
keyP            :   OUT STD_LOGIC);

END Lab_7_Keypad;

ARCHITECTURE a OF Lab_7_Keypad IS   
TYPE STATE_TYPE IS ( Col1Set, Col2Set, Col3Set, Col4Set );
SIGNAL  coltest :   STATE_TYPE;

BEGIN
PROCESS (clk, nReset )
BEGIN
keyP <= '0';
Col <= "1111";
IF nReset = '0' THEN                        --  asynch Reset to zero
    coltest <=  Col1Set;
    Col <="1111";
    keyP <= '0';
ELSIF clk'EVENT AND clk = '1' THEN          --  triggers on PGT

    CASE coltest IS
        WHEN Col1Set => 
        Col <="1110";
            CASE row IS
                WHEN    "1110"=>--row 1
                data <= "0001";
                keyP <= '1';
                WHEN    "1101"=>--row 2
                data <= "0100";
                keyP <= '1';
                WHEN    "1011"=>--row 3
                data <= "0111";
                keyP <= '1';
                WHEN    "0111"=>--row 4
                data <= "1110";
                keyP <= '1';
                WHEN OTHERS => coltest <= Col2Set;
            END CASE;
    --Continues for another couple Case statements for the extra columns