Electrical – VHDL simulation shows ‘u’ by read the input

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;


entity TestRun01 is
    Port ( Clk : in  STD_LOGIC;
           Din : in  STD_LOGIC;
           Dout : out  STD_LOGIC_vector(11 downto 0));
end TestRun01;

architecture Behavioral of TestRun01 is

signal regr : std_logic_vector(11 downto 0) :="000000000010"; 
signal reg  : std_logic;

begin

    process(Clk,reg)

    begin
        if falling_edge(CLK) then

            if Din ='1' then
                reg <='1';
            elsif  Din='0' then
                reg <='0';
            else
                reg <= reg;
            end if;

regr<=regr(10 downto 0) & '0';
regr(0)<=reg;   

        end if;

    end process;

    Dout<=regr;

end Behavioral;

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY Test1 IS
END Test1;

ARCHITECTURE behavior OF Test1 IS 


    COMPONENT TestRun01
    PORT(
         Clk : IN  std_logic;
         Din : IN  std_logic;
         Dout : OUT  std_logic_vector(11 downto 0)
        );
    END COMPONENT;



   signal Clk : std_logic := '0';
   signal Din : std_logic := '0';


   signal Dout : std_logic_vector(11 downto 0);

   -- Clock period definitions
   constant Clk_period : time := 10 ns;

BEGIN

    -- Instantiate the Unit Under Test (UUT)
   uut: TestRun01 PORT MAP (
          Clk => Clk,
          Din => Din,
          Dout => Dout
        );

   -- Clock process definitions
   Clk_process :process
   begin
        Clk <= '0';
        wait for Clk_period/2;
        Clk <= '1';
        wait for Clk_period/2;
   end process;


   -- Stimulus process
   stim_proc: process
   begin
--      wait for 1 ns;  
        Din <= '1';
        wait for Clk_period/2;
        Din <= '0';
        wait for Clk_period/2;
        Din <= '0';
        wait for Clk_period/2;
        Din <= '1';
        wait for Clk_period/2;
   end process;

END;

Why there's a U?
And how can I get rid of it?