VHDL – How to Use ‘if’ for Variable Comparison

comparisonifvhdl

Using Xilinx, I need to compare a 'variable' called 'row', defined as:

variable row   : std_logic_vector(2 * n - 1 downto 0);

This line was given to me, now I need an if statement that will execute if row is = 1.

I have tried:

if (row = "1") then

but the IDE warns me that this condition will always result in false? which should not happen.

If I try if (row = '1') then or if (row = 1) then then I get the error:

found '0' definitions of operator "="

Googling this, the only suggestion is to include libraries that I have already included:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

Best Answer

Your variable is a std_logic_vector and you compare it to an integer. You have to cast the std_logic_vector like this:

if(to_integer(signed(row)) = 1) or if(to_integer(unsigned(row)) = 1)

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VHDL variable behaving strangely

You don't say what you want the code to do, but I can see a couple of trouble areas. The first is that you don't have any reset logic in your process. It's important to make sure that you properly initialize everything in order to prevent unusual operation. This however is not likely the cause of your trouble.

What I think is causing the incorrect operation is that you are looking for the clock signal to be high instead of checking for the clock to transition from a low to high. This is called the "rising edge" of the clock. Synchronous logic operates on clock edges rather than clock levels.

You mention that you should not have to look for a rising edge since the clock is in the sensitivity list, and thus if your process is executed you can only check the level of the clock. This may be theoretically true but synthesis tools work by inferring logic from the language used to describe it. Most synthesis tools I have used are designed to produce correct logic when described below.

process(clock, reset)

variable counter : std_logic_vector (15 downto 0) :=  x"0000";
variable op : std_logic_vector (7 downto 0);

begin

if reset = '1' then
    -- reset everything to a known state here

elsif rising_edge(clock) then
    op := cw(15 downto 8);

    if op = x"20" then
        counter := counter + cw(7 downto 0);
    end if;

    counter := counter + 2;
    ia <= counter;
end if;
end process;

Writing good HDL is just as much about getting the logic correct as it is describing it in the way the synthesis tools are expecting to see it. If you decide "it's the same thing" and write things in a non-standard way you may well find that the simulator tells you one thing but the synthesizer fails to see it the same way. This is a fine point to learn, and one that can cause you a lot of headache and frustration should you decide otherwise.

Using a Counter to Determine next MSB position in polynomial division

I assume that ctr_reg is of type (un)signed because it's a counter.

VHDL expect normal indices to be of type integer (natural, positive are subtypes of integer). See the definition for std_logic_vector:

type STD_LOGIC_VECTOR is array (NATURAL range <>) of STD_LOGIC;

So you must convert your counter from (un)signed to integer:

if (numerator(to_integer(ctr_reg)) = '1') then

If ctr_reg is of type std_logic_vector (slv), then you must also convert slv to unsigned:

if (numerator(to_integer(unsigned(ctr_reg))) = '1') then

If this construct is to long, write a function (let's say to_index(..)) which hides these conversions :)

if (numerator(to_index(ctr_reg)) = '1') then

A definition for to_index(..) can be found here.

Edit 1:

List of commonly used packages in VHDL:

library IEEE;
use     IEEE.STD_LOGIC_1164.ALL;  -- common std_logic(_vector) operations
use     IEEE.NUMERIC_STD.ALL;     -- defines signed and unsigned and their operations

Best Answer

Related Solutions

VHDL variable behaving strangely

Using a Counter to Determine next MSB position in polynomial division

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