Electronic – Nesting Elseif, If, Else in VHDL

ifvhdl

In the code below, I want to pull out statements surrounding the the ** asterisks ** below.

stateS0 = 1' and o_done = '1'

and

o_done = '1' and stateS0 = '0'

into separate comparisons using if or elseif.

I am struggling at how to pull out and compare if I am in state S0 and o_done = 1 and I am in state 1 and o_done = 1 into seperate if, then, else, elsif statements.

        process begin
        wait until rising_edge(clk);
        if (reset = '1') then
          stuff;
        else
          **if( StateS0 = '1' AND o_done = '1' ) then**
            stuff;
          elsif( ...stuff... ) then
            stuff;
          end if;
        end if;
      end process;
    
       
      process begin
        wait until rising_edge(clk);
        if (reset = '1') then
          o_done <= '0';
        else
          if ( ...stuff ...) then
            o_done <= '1';
          **elsif ( o_done = '1' AND StateS0 = '0' ) then**
            o_done <= '1';
          else
            o_done <= '0';
          end if;
        end if;
      end process;

I was thinking something like:

if stateS0=0 then if
o_done='1' then...

if o_done='1' then if
stateS0='1' then...

but can you do…

process begin
    wait until rising_edge(clk);
    if (reset = '1') then
      stuff;
    else
    if( state0 = '1') then
        if o_done='1' then
                stuff;
        end if;
    end if;
      elsif( stuff ) then
                stuff;
    end if;
  end process;

is that legal code ?

Or is this legal ?

  process begin
    wait until rising_edge(clk);
    if (reset = '1') then
      o_done <= '0';
    else
      if ( stuff ) then
        o_done <= '1';
      elsif ( o_done = '1') then
       if state0 = '0' ) then
        o_done <= '1';
      else
        o_done <= '0';
      end if;
    end if;
  end process;

But I am not sure about if I am nesting these right. Can you nest an:

if
if
end if
end if

within after an elsif or else ?

Can you nest elseif in if, then else statements ? Or elseif only check 0 or 1 conditions and not combinatorial conditions like if then else can ?

Best Answer

Can you nest elseif in if, then else statements ?

You are certainly allowed to nest "if" statements inside each-other. This is perfectly legal code.

if boolean_expression_1 then
    if boolean_expression_1a then
      --some statements
    elsif boolean_expression_1b then
      --some statements
    elsif boolean_expression_1c then
      --some statements
    else
      --some statements
    end if;
    --some statements
elsif boolean_expression_2 then
    if boolean_expression_2a then
      --some statements
    elsif boolean_expression_2b then
      --some statements
    else
      --some statements
    end if;
else boolean_expression_3 then
    --some statements
end if;

Or elseif only check 0 or 1 conditions and not combinatorial conditions like if then else can ?

The types of expressions you can put after "elsif" are exactly the same as for "if".

As for your code. if the type of o_done is a character type that has '1' and '0' as possible values, and State0 and State1 are both booleans then the following should compile without problems.

  if ( State1 ) then
    o_done <= '1';
  elsif (o_done = '1' AND State0 ) then
    o_done <= '1';
  else
    o_done <= '0';
  end if;

This is also legal

if state=s0 then 
    if o_done='1' then
      --some statements here
    end if;
end if;

if o_done='1' then
  if  stateS1='1' then
    --some statements here
  end if;
end if;

Related Solutions

Electronic – Difference between If-else and Case statement in VHDL

Can anyone tell me the difference between If-Else construct and Case statement constructs of a process in VHDL in terms of how the code is inferenced into RTL circuit by the synthesis tool ?

The if-elsif-else construct infers a priority routing network:

schematic

^{simulate this circuit – Schematic created using CircuitLab}

This corresponds to

if bool_expr_1 then
    sig <= val_expr_1;
elsif bool_expr_2 then
    sig <= val_expr_2;
elsif bool_expr_3 then
    sig <= val_expr_3;
else
    sig <= val_expr_4;
end if;

The case construct, on the other hand, infers a big ol' mux:

enter image description here

This corresponds to

case case_expr is
  when c0 =>
    sig <= val_expr_0;
  when c1 =>
    sig <= val_expr_1;
  when c2 =>
    sig <= val_expr_2;
      ...
  when others =>
    sig <= val_expr_N;
end case;

Obviously these are very simplified designs with only one value expression, resulting in one output.

Do consider the case of multiple nested if-else and mixing case-statements with if-else construct inside a process.

Per the above, you can see how they would nest/mix.

Also when to use which construct ?

Since if-else infers priority, it should be used when more than one input condition could occur. Using case, one the other hand, is appropriate when the inputs are mutually exclusive.

Electronic – Why is the simple counter VHDL not working? Where did the signals go

the rising_edge() parameter is only really for clock signals. One option would be the following:

clk_proc: process( clk, switch1, switch0 )
begin
    if switch1 = '1' then
        counter <= ( others => '0' );
    elseif rising_edge( clk ) then
        if switch0 = '1' then
            counter <= counter + 1;
        end if;
    end if;
end process;

This is known as an asynchronously reset process, which means that it'll reset the counter whenever reset (switch1) is high, regardless of clock state. A synchronously reset process would look the same as your second example:

clk_proc: process( clk, switch1, switch0 )
begin
    if rising_edge( clk ) then
        if switch1 = '1' then
            counter <= ( others => '0' );
        elsif switch0 = '1' then
            counter <= counter + 1;
        end if;
    end if;
end process;

You did state though that your second example didn't work as expected. My suspicion is that this is because the signals driving it are switches rather than clocked logic signals. Switches don't actually switch instantaneously, instead bouncing between on and off a few times before settling. You need to implement some sort of debounce process to produce a signal which is synchronous with your clock and can control your timer.

It's also worth mentioning that FPGA design is a lot easier if you simulate stuff first. Xilinx ISE includes a simulator - create a testbench and use it! That lets you easily see what's happening in your implementation before you ever get near hardware.

Best Answer

Related Solutions

Electronic – Difference between If-else and Case statement in VHDL

Electronic – Why is the simple counter VHDL not working? Where did the signals go

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