Nesting entities in VHDL (Altera Quartus)

Looking at an entity, how can one determine the actual architectural model being used without hints from the architecture name?

You can't - when it is instantiated or configured the architecture can be specified (if there is more than one to choose from) or a default will be chosen for you.

If specifying multiple architectures for a single entity (which I understand is possible) do you simply give the architectures different names in the same file or...?

You give them different names. It doesn't have to be within the same file (in fact VHDL cares a lot less than you might think about what's in what file)

Are the architecture names confined to a given entity (that is, is there any problem with "namespaces" by using the same architecture name over multiple entities)?

They are "attached" to an entity, so can be reused.

I often use a1 as my architecture for everything synthesisable as

• rtl implies lower level (to many readers) than I write at.
• behavioural often implies non-synthesisable (to some readers)
• synth is used by the synthesiser for it's model (otherwise I'd have used that)

a1 has been non-conflicted so far and doesn't cause confusion ;)

If I actually have more than one architecture, I tend to name them verbosely (for example hard_multipliers and lut_multipliers for a filter which instantiates - or not - MUL18 blocks).

Very often you only have one architecture, so it doesn't matter. Good entity names are much more important.

It seems there is a distinction between RTL and behavioral, but as mentioned above I'm not really seeing it in the examples I've seen (often I only see one architecture being defined). Is one architecture more common than the others?

It's historical - you didn't used to be able to synthesise "behavioural" code (which at one point included things like adding!) - so you created an RTL version which instantiated adders and the like. (That's as I understand it - I've been writing behavioural (and yet still synthesisable) code since I started VHDLing in about 1999!)

VHDL accepts the ISO 8859-1 character set, this is UTF-8.

Your VHDL analyzer is having problems with some of the characters as a result of you copying the text directly from a book.

Your comments aren't delineated by two dashes (e.g. --), your double quotation marks all need to be replaced with ".

After which the VHDL code analyzes.

There's no discernible reason why d3, d2, d1, and d0 can't be replaced with a bit_vector. There may uses with the present port interface in the book.

Formal ports are associated with actual signals in an association list. It's possible to associate individual elements of a vector with a base element.

Converting between non-closely related types can be done with conversion routines:

-- bcd_7seg.vhd
-- bcd-to-seven-segment decoder
entity bcd_7seg is
    port(
    d3, d2, d1, d0: in bit;
    a, b, c, d, e, f, g: out bit
    );
end entity;
architecture seven_segment of bcd_7seg is
    signal input : bit_vector (3 downto 0);
    signal output: bit_vector (6 downto 0);
begin
    input <= d3 & d2 & d1 & d0;
    with input select
        output <= "0000001" when "0000",
                  "1001111" when "0001",
                  "0010010" when "0010",
                  "0000110" when "0011",
                  "1001100" when "0100",
                  "0100100" when "0101",
                  "1100000" when "0110",
                  "0001111" when "0111",
                  "0000000" when "1000",
                  "0001100" when "1001",
                  "1111111" when others;
-- separate the output vector to make individual pin outputs.
    a <= output(6);
    b <= output(5);
    c <= output(4);
    d <= output(3);
    e <= output(2);
    f <= output(1);
    g <= output(0);
end architecture;

library ieee;
use ieee.std_logic_1164.all;

entity bcd_tb is
end entity;

architecture foo of bcd_tb is
    signal d:  std_logic_vector (3 downto 0) := "0100";
    signal output:    std_logic_vector (6 downto 0);
begin
DUT:
    entity work.bcd_7seg
        port map (
            d3 => to_bit(d(3)),
            d2 => to_bit(d(2)),
            d1 => to_bit(d(1)),
            d0 => to_bit(d(0)),
            to_stdulogic(a) => output(6),
            to_stdulogic(b) => output(5),
            to_stdulogic(c) => output(4),
            to_stdulogic(d) => output(3),
            to_stdulogic(e) => output(2),
            to_stdulogic(f) => output(1),
            to_stdulogic(g) => output(0)
        );
end architecture;

You can also associate individual elements of an array type port with the base element type or use conversion functions as are shown above for converting between type bit and the element type for std_logic_vector.