Electronic – VHDL: Architecture naming and interpretation

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Note: I am using Xilinx's ISE and have an FPGA board to work with (with switches and lights and so on), and I've hacked together some simple projects so far. At the same time I'm reading several tutorials to build a foundation for what I'm doing.

I've seen various entities and their architectures mentioned in the reference materials I've been going through, but the naming is often confusing. Often instead of "architecture rtl of.." or "architecture structural of…" I'll see "architecture foo of…" or even "architecture arch of…"

I realize (belatedly) that the architecture name is just as arbitrary as the entity naming, though there are style guides that suggest more consistent naming conventions can be used to avoid this issue. This leads me to a few questions:

  • Looking at an entity, how can one determine the actual architectural
    model being used without hints from the architecture name? RTL,
    behavioral, structural… they appear to be quite similar to my
    learner's eye (assuming the examples I've seen were actually named
    correctly). A simple but obvious example would be helpful here (or a
    pointer to one).

  • If specifying multiple architectures for a single entity (which I
    understand is possible) do you simply give the architectures
    different names in the same file or…?

  • Are the architecture names confined to a given entity (that is, is
    there any problem with "namespaces" by using the same architecture
    name over multiple entities)?

Edit: and one more:

  • It seems there is a distinction between RTL and behavioral, but as mentioned above I'm not really seeing it in the examples I've seen (often I only see one architecture being defined). Is one architecture more common than the others?

What I've been looking for is a comprehensive yet simple multi-component project (little components), written using best practices (proper naming, not all crammed into one file, etc.) but I've yet to find one. I find properly crafted sample projects very useful for illuminating basic principles and best practices. If you know of such an example project I'd be grateful for a pointer to that as well. (If nothing else, perhaps once I figure this out I can share one of my own…)

Best Answer

Looking at an entity, how can one determine the actual architectural model being used without hints from the architecture name?

You can't - when it is instantiated or configured the architecture can be specified (if there is more than one to choose from) or a default will be chosen for you.

If specifying multiple architectures for a single entity (which I understand is possible) do you simply give the architectures different names in the same file or...?

You give them different names. It doesn't have to be within the same file (in fact VHDL cares a lot less than you might think about what's in what file)

Are the architecture names confined to a given entity (that is, is there any problem with "namespaces" by using the same architecture name over multiple entities)?

They are "attached" to an entity, so can be reused.

I often use a1 as my architecture for everything synthesisable as

  • rtl implies lower level (to many readers) than I write at.
  • behavioural often implies non-synthesisable (to some readers)
  • synth is used by the synthesiser for it's model (otherwise I'd have used that)

a1 has been non-conflicted so far and doesn't cause confusion ;)

If I actually have more than one architecture, I tend to name them verbosely (for example hard_multipliers and lut_multipliers for a filter which instantiates - or not - MUL18 blocks).

Very often you only have one architecture, so it doesn't matter. Good entity names are much more important.

It seems there is a distinction between RTL and behavioral, but as mentioned above I'm not really seeing it in the examples I've seen (often I only see one architecture being defined). Is one architecture more common than the others?

It's historical - you didn't used to be able to synthesise "behavioural" code (which at one point included things like adding!) - so you created an RTL version which instantiated adders and the like. (That's as I understand it - I've been writing behavioural (and yet still synthesisable) code since I started VHDLing in about 1999!)

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