Electronic – VHDL impure keyword

best practicevhdl

I have vhdl code along these lines (explanation below):

architecture arc of anEntity is
  signal x1_sig : T;
  signal x2_sig : T2;

  function test(x1: T, x2: T2) return boolean is
  begin
    if complicatedConditionWith x1 and x2 then
        return true;
    else
        return false;
    end if;
  end function;
begin
  p1: process (...) is
    impure function test return boolean is
    begin
      return test(x1_sig,x2_sig);
    end function;
  begin
    ...
    if test then --occurs several times
    ...
  end process;
end architecture;

For ease of writing and readability I put a complicated condition into a function. Since I am lazy and always use the same signals with that function, I added a shorthand to the process were I use this function mainly. However modelsim complained about accesses to a signal from a pure function, so I added the impure modifier. To my knowledge this is telling the compiler that the function might have side effects, even though, since I access everything only reading (in c one could define the function parameters as const) I consider my function free of side effects.
Might the addition of impure have negative side effects on the synthesis result?

Best Answer

A "pure" function, as well as having no side effects, also returns the same result every time it is evaluated with the same arguments. The importance of this is to allow optimisations : the compiler is permitted to cache the result, compute it outside the inner loop, reorder computations etc without affecting correctness.

A function that reads a signal (if you were updating it, that would be a side effect!) will return results depending on that signal value, therefore it cannot be pure. Declaring it impure is correct and will not affect synthesis results.

(Arguably better is to keep it pure and pass in the signal as a parameter; however if that adds clutter and hinders readability, the current approach is better)

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