Electrical – VHDL: Using internal signals in testbench

testbenchvhdl

I'm trying to use one of my design's internal signals in my testbench. I already know how I would do it in Verilog:

Goertzel i1 (
// port map - connection between master ports and signals/registers   
);
.
.
.
always @ (posedge i1.en) //do something

en is the enable signal I generate in my sistem, it is a signal declared in the top module, which is created in one element of the system, and then distributed to some of the other elements via port maps.

So, in VHDL testbench, I want to do something like:

uut: Goertzel PORT MAP (
          RST => RST_s,
          CLK => CLK_s,
          X => X_s,
          Y1 => Y1_s,
          Y2 => Y2_s
        );
.
.
.
wait until "/goertzel_tb/uut/en/" = '1';  //path to variable, read in Questa

What is the correct syntax? Or is there a way to do this?

EDIT: Tried this:
Declared spy_en signal within TB file, and then did:

spy_en <= << signal.goertzel_tb.Goertzel.en : std_logic >>;

Questa gives errors.

Best Answer

Not exactly what I was looking for, but it does the trick as it should! How can I get internal signals to testbench in VHDL 97 and ISim?

Related Solutions

Electronic – clock in testbench VHDL

First, note that all processes run concurrently with one another. So to have a clock driving your other processes, you want its code in its own process. The code inside the process runs sequentially, and this is how you are able to generate a clock signal with a specific period (using 'wait' statements). A process with a sensitivity list will run whenever one of these signals changes. However, a process with no sensitivity list will always be running. It is up to you to decide when it runs. This is where 'wait' statements come in handy. As a side note, you can't use 'wait' statements in a process with a sensitivity list.

You can implement a simple flip-flop by using either of the two codes below.

process (clk) is
begin
    if clk = '1' then
        Q<=D;
    end if;
end process;


process is
begin
    wait until clk = '1' and clk'event;
    Q<=D;
end process;

Notice how in one design, the process only initiates when there is an event on clk, where it then checks the level. The second process runs continuously, but it waits for an event and level high.

Now, these processes are dependent on the clock. To simulate a clock, we only want the clock to be dependent on time. After half the period we want to toggle the level. So you have a process with no sensitivity list, and the wait statements wait for a certain amount of time before changing the level of the clock.

Hope that helps!

Note: The syntax might be slightly off on those examples, it's been a while since I generated any code..

Electrical – Displaying signals in testbench from counter VHDL

This isn't a VHDL question but a tool question. The details may vary from one simulator to another but typically there's a tree view showing the testbench and all components in it - and components inside them, recursively.

Select the component you're interested in, and its internal signals will appear in the signal list view. Select some or all of those signals and there will be some means (right click?) to add them to the Wave window.

Now re-start and re-run the simulation.

(If that's not detailed enough, look at manuals, tutorials, or tell us which simulator you're using. GHDL- which is command-line based - has a command line option to collect all signals, then you select the ones you want in GTKWave)

Best Answer

Related Solutions

Electronic – clock in testbench VHDL

Electrical – Displaying signals in testbench from counter VHDL

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