There are some typical errors that you should understand and avoid first.
When creating your process instantiating your register you didn't specify any sensitivity list. (If you don' t know what it is check there.) Since your process is synchronous to your clock CLK you need to put it into the sensitivity list.
Another thing that might be useful (it 's more a suggestion than a real mistake) is to put any of your register's reset signal asynchronous (at least in the process) and if you want it synchronous you can still synchronize it at the top level. It will take fewer elements to implement this.
process (RST, CLK)
begin
if (RST = '0') then
D_OUT <= B"0000_0000_0000";
elsif (rising_edge (CLK)) then
if (EN = '1') then
D_OUT <= D_IN;
end if;
end if;
end process;
Then , in your testbench, like @scary_jeff commented, you didn't make your clock change its state. So your rising_edge condition is only valid one time.
To avoid this I suggest that you always create a process apart generating your clock.
clk_gen : process (CLK)
begin
clk <= not clk after clk_period/2;
end process;
(Don't forget to initialize your clock)
Since you didn't really specify what problem you had in simulation I can't help more for now but you should try this first and come back with more information.
Two ways are commonly used:
Stop the clock (or clocks). That way there are no more events, and the simulation stops. Sometimes, there is a signal (for instance called done) that turns of the clock generator. The testbench asserts the done signal when all tests are completed.
Report a failure. This is not so elegant, but many people use it. A severity of failure will cause the simulator to stop.
report "simulation finished successfully" severity FAILURE;
Stop procedure A third way, only available since VHDL 2008 is to call the procedure stop, in the env package of the std library. For instance, like this: std.env.stop;
Best Answer
This isn't a VHDL question but a tool question. The details may vary from one simulator to another but typically there's a tree view showing the testbench and all components in it - and components inside them, recursively.
Select the component you're interested in, and its internal signals will appear in the signal list view. Select some or all of those signals and there will be some means (right click?) to add them to the Wave window.
Now re-start and re-run the simulation.
(If that's not detailed enough, look at manuals, tutorials, or tell us which simulator you're using. GHDL- which is command-line based - has a command line option to collect all signals, then you select the ones you want in GTKWave)